mfreq.v

来自「verilog编写基于FPGA的示波器核心实现」· Verilog 代码 · 共 39 行

module mfreq(
				clk_in,
				clk_out
				);
input clk_in;
output reg clk_out;

parameter N=8;

reg[7:0] count;

always @(posedge clk_in)
begin
if (count==(N-1))
 count<=0;
else
 count<=count+1;
end

always
begin
 if (N<=2)
 clk_out=count[0];
 else if (N<=4)
 clk_out=count[1];
 else if (N<=8)
 clk_out=count[2];
 else if (N<=16)
 clk_out=count[3];
 else if (N<=32)
 clk_out=count[4];
 else if (N<=64)
 clk_out=count[5];
 else if (N<=128)
 clk_out=count[6];
 else if (N<=256)
 clk_out=count[7];
end
endmodule