dds.hier_info

verilog编写基于fpga的DDS实现

address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
rden_b => ram_block1a8.PORTBRE
rden_b => ram_block1a9.PORTBRE
rden_b => ram_block1a10.PORTBRE
rden_b => ram_block1a11.PORTBRE
rden_b => ram_block1a12.PORTBRE
rden_b => ram_block1a13.PORTBRE
rden_b => ram_block1a14.PORTBRE
rden_b => ram_block1a15.PORTBRE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.ENA0


|dds|square:inst2
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]


|dds|square:inst2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_b431:auto_generated.address_a[0]
address_a[1] => altsyncram_b431:auto_generated.address_a[1]
address_a[2] => altsyncram_b431:auto_generated.address_a[2]
address_a[3] => altsyncram_b431:auto_generated.address_a[3]
address_a[4] => altsyncram_b431:auto_generated.address_a[4]
address_a[5] => altsyncram_b431:auto_generated.address_a[5]
address_a[6] => altsyncram_b431:auto_generated.address_a[6]
address_a[7] => altsyncram_b431:auto_generated.address_a[7]
address_a[8] => altsyncram_b431:auto_generated.address_a[8]
address_a[9] => altsyncram_b431:auto_generated.address_a[9]
address_a[10] => altsyncram_b431:auto_generated.address_a[10]
address_a[11] => altsyncram_b431:auto_generated.address_a[11]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_b431:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_b431:auto_generated.q_a[0]
q_a[1] <= altsyncram_b431:auto_generated.q_a[1]
q_a[2] <= altsyncram_b431:auto_generated.q_a[2]
q_a[3] <= altsyncram_b431:auto_generated.q_a[3]
q_a[4] <= altsyncram_b431:auto_generated.q_a[4]
q_a[5] <= altsyncram_b431:auto_generated.q_a[5]
q_a[6] <= altsyncram_b431:auto_generated.q_a[6]
q_a[7] <= altsyncram_b431:auto_generated.q_a[7]
q_a[8] <= altsyncram_b431:auto_generated.q_a[8]
q_a[9] <= altsyncram_b431:auto_generated.q_a[9]
q_a[10] <= altsyncram_b431:auto_generated.q_a[10]
q_a[11] <= altsyncram_b431:auto_generated.q_a[11]
q_b[0] <= <GND>


|dds|square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6