dds.hif

verilog编写基于fpga的DDS实现

Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1760
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
C:|altera|megacore|ed8b10b-v1.6.1|lib|
C:|altera|megacore|
C:|Documents and Settings|Administrator|桌面|b|
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
mux_ogc
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# case_insensitive
# source_file
db|mux_ogc.tdf
8d99597912852ec8f9b9e791f6cfb35f
6
# used_port {
sel1
-1
3
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data47
-1
3
data46
-1
3
data45
-1
3
data44
-1
3
data43
-1
3
data42
-1
3
data41
-1
3
data40
-1
3
data4
-1
3
data39
-1
3
data38
-1
3
data37
-1
3
data36
-1
3
data35
-1
3
data34
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated
}
# end
# entity
altsyncram_b431
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# case_insensitive
# source_file
db|altsyncram_b431.tdf
c21b212927cd3a4c607a51be66b773c
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
squra.mif
27799344959ad99c0cc3159e7ea053
}
# hierarchies {
square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated
}
# end
# entity
altsyncram_ut41
# storage
db|dds.(23).cnf
db|dds.(23).cnf
# case_insensitive
# source_file
db|altsyncram_ut41.tdf
eaa5f7e448d4df80328deff82a9a16
6
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated
}
# end
# entity
altsyncram_4pi2
# storage
db|dds.(24).cnf
db|dds.(24).cnf
# case_insensitive
# source_file
db|altsyncram_4pi2.tdf
6f3980cadaa01efe83257fcbf1dbc06a
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cos.mif
d60b31b8e6eb39847a3bc929739f3ee
}
# hierarchies {
cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|altsyncram_4pi2:altsyncram1
}
# end
# entity
altsyncram_3u41
# storage
db|dds.(29).cnf
db|dds.(29).cnf
# case_insensitive
# source_file
db|altsyncram_3u41.tdf
c5349168bffc62537dab883d8849ce1
6
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
sin_rom:inst|altsyncram:altsyncram_component|altsyncram_3u41:auto_generated
}
# end
# entity
altsyncram_9pi2
# storage
db|dds.(30).cnf
db|dds.(30).cnf
# case_insensitive
# source_file
db|altsyncram_9pi2.tdf
d4989f480d34752b697eff6ce8b6d6c
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sin.mif
1a856388b78d1b28ae12dbdaaedc6fd4
}
# hierarchies {
sin_rom:inst|altsyncram:altsyncram_component|altsyncram_3u41:auto_generated|altsyncram_9pi2:altsyncram1
}
# end
# entity
decode_ogi
# storage
db|dds.(35).cnf
db|dds.(35).cnf
# case_insensitive
# source_file
db|decode_ogi.tdf
ffc7173ea4e253ca8971cc1a77d92062
6
# used_port {
eq7
-1
3
eq6
-1
3
eq5
-1
3
eq4
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# end
# entity
altsyncram_90m1
# storage
db|dds.(44).cnf
db|dds.(44).cnf
# case_insensitive
# source_file
db|altsyncram_90m1.tdf
3d5b161fca4406933a84c32d359ea8b
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
mux4
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# case_insensitive
# source_file
mux4.tdf
efe193d1bc1bf47a1e8f82b5f0e12c
6
# used_port {
sel1
-1
3
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data3x9
-1
3
data3x8
-1
3
data3x7
-1
3
data3x6
-1
3
data3x5
-1
3
data3x4
-1
3
data3x3
-1
3
data3x2
-1
3
data3x11
-1
3
data3x10
-1
3
data3x1
-1
3
data3x0
-1
3
data2x9
-1
3
data2x8
-1
3
data2x7
-1
3
data2x6
-1
3
data2x5
-1
3
data2x4
-1
3
data2x3
-1
3
data2x2
-1
3
data2x11
-1
3
data2x10
-1
3
data2x1
-1
3
data2x0
-1
3
data1x9
-1
3
data1x8
-1
3
data1x7
-1
3
data1x6
-1
3
data1x5
-1
3
data1x4
-1
3
data1x3
-1
3
data1x2
-1
3
data1x11
-1
3
data1x10
-1
3
data1x1
-1
3
data1x0
-1
3
data0x9
-1
3
data0x8
-1
3
data0x7
-1
3
data0x6
-1
3
data0x5
-1
3
data0x4
-1
3
data0x3
-1
3
data0x2
-1
3
data0x11
-1
3
data0x10
-1
3
data0x1
-1
3
data0x0
-1
3
}
# include_file {
..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
}
# hierarchies {
mux4:inst3
}
# end
# entity
lpm_mux
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# case_insensitive
# source_file
..|..|altera|quartus60|libraries|megafunctions|lpm_mux.tdf
9bf66e437b499c0f0b81c977a5a50
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
12
PARAMETER_UNKNOWN
USR
LPM_SIZE
4
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
2
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_ogc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
sel1
-1
3
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data3_9
-1
3
data3_8
-1
3
data3_7
-1
3
data3_6
-1
3
data3_5
-1
3
data3_4
-1
3
data3_3
-1
3
data3_2
-1
3
data3_11
-1
3
data3_10
-1
3
data3_1
-1
3
data3_0
-1
3
data2_9
-1
3
data2_8
-1
3
data2_7
-1
3
data2_6
-1
3
data2_5
-1
3
data2_4
-1
3
data2_3
-1
3
data2_2
-1
3
data2_11
-1
3
data2_10
-1
3
data2_1
-1
3
data2_0
-1
3
data1_9
-1
3
data1_8
-1
3
data1_7
-1
3
data1_6
-1
3
data1_5
-1
3
data1_4
-1
3
data1_3
-1
3
data1_2
-1
3
data1_11
-1
3
data1_10
-1
3
data1_1
-1
3
data1_0
-1
3
data0_9
-1
3