altsyncram_3u41.tdf

verilog编写基于fpga的DDS实现

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="YES" INIT_FILE="sin.mif" INSTANCE_NAME="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=4096 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=12 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 6.0 cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION altsyncram_9pi2 (address_a[11..0], address_b[11..0], clock0, clock1, data_b[11..0], wren_b)
RETURNS ( q_a[11..0], q_b[11..0]);
FUNCTION sld_mod_ram_rom (data_read[11..0])
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[11..0], data_write[11..0], enable_write, tck_usr);

--synthesis_resources = M4K 192 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_3u41
( 
	address_a[11..0]	:	input;
	clock0	:	input;
	q_a[11..0]	:	output;
) 
VARIABLE 
	altsyncram1 : altsyncram_9pi2;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "000000000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 0,
			NUMWORDS = 4096,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 12,
			WIDTHAD = 12
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE