dds.tan.qmsg

verilog编写基于fpga的DDS实现

{ "Info" "ITDB_FULL_TPD_RESULT" "select\[0\] output\[3\] 18.155 ns Longest " "Info: Longest tpd from source pin \"select\[0\]\" to destination pin \"output\[3\]\" is 18.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns select\[0\] 1 PIN PIN_144 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_144; Fanout = 18; PIN Node = 'select\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { select[0] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 456 320 488 472 "select\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.502 ns) + CELL(0.292 ns) 10.263 ns mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[3\]~544 2 COMB LC_X21_Y13_N8 1 " "Info: 2: + IC(8.502 ns) + CELL(0.292 ns) = 10.263 ns; Loc. = LC_X21_Y13_N8; Fanout = 1; COMB Node = 'mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[3\]~544'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.794 ns" { select[0] mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~544 } "NODE_NAME" } } { "db/mux_ogc.tdf" "" { Text "F:/fpga test/dds/db/mux_ogc.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.292 ns) 11.790 ns mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[3\]~545 3 COMB LC_X21_Y11_N8 1 " "Info: 3: + IC(1.235 ns) + CELL(0.292 ns) = 11.790 ns; Loc. = LC_X21_Y11_N8; Fanout = 1; COMB Node = 'mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[3\]~545'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.527 ns" { mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~544 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~545 } "NODE_NAME" } } { "db/mux_ogc.tdf" "" { Text "F:/fpga test/dds/db/mux_ogc.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.241 ns) + CELL(2.124 ns) 18.155 ns output\[3\] 4 PIN PIN_21 0 " "Info: 4: + IC(4.241 ns) + CELL(2.124 ns) = 18.155 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'output\[3\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.365 ns" { mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~545 output[3] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 304 1160 1336 320 "output\[11..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.177 ns ( 23.01 % ) " "Info: Total cell delay = 4.177 ns ( 23.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.978 ns ( 76.99 % ) " "Info: Total interconnect delay = 13.978 ns ( 76.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.155 ns" { select[0] mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~544 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~545 output[3] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "18.155 ns" { select[0] select[0]~out0 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~544 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[3]~545 output[3] } { 0.000ns 0.000ns 8.502ns 1.235ns 4.241ns } { 0.000ns 1.469ns 0.292ns 0.292ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[10\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 2.616 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[10\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.616 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.388 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 526 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 526; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.677 ns) + CELL(0.711 ns) 5.388 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[10\] 2 REG LC_X23_Y13_N1 2 " "Info: 2: + IC(4.677 ns) + CELL(0.711 ns) = 5.388 ns; Loc. = LC_X23_Y13_N1; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[10\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.388 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.20 % ) " "Info: Total cell delay = 0.711 ns ( 13.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.677 ns ( 86.80 % ) " "Info: Total interconnect delay = 4.677 ns ( 86.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.388 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.388 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10] } { 0.000ns 4.677ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.787 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y13_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.478 ns) + CELL(0.309 ns) 2.787 ns sld_hub:sld_hub_inst\|sld_