dds.tan.qmsg

verilog编写基于fpga的DDS实现

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "wrclock memory ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_datain_reg0 memory ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_memory_reg0 197.01 MHz 5.076 ns Internal " "Info: Clock \"wrclock\" has Internal fmax of 197.01 MHz between source memory \"ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_datain_reg0\" and destination memory \"ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_memory_reg0\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_datain_reg0 1 MEM M4K_X19_Y5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y5; Fanout = 1; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_datain_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_memory_reg0 2 MEM M4K_X19_Y5 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X19_Y5; Fanout = 0; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_memory_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock destination 3.167 ns + Shortest memory " "Info: + Shortest clock path from clock \"wrclock\" to destination memory is 3.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wrclock 1 CLK PIN_28 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 42; CLK Node = 'wrclock'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 624 320 488 640 "wrclock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.708 ns) 3.167 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_memory_reg0 2 MEM M4K_X19_Y5 0 " "Info: 2: + IC(0.990 ns) + CELL(0.708 ns) = 3.167 ns; Loc. = M4K_X19_Y5; Fanout = 0; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_memory_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.698 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 68.74 % ) " "Info: Total cell delay = 2.177 ns ( 68.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.26 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.167 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.167 ns" { wrclock wrclock~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock source 3.181 ns - Longest memory " "Info: - Longest clock path from clock \"wrclock\" to source memory is 3.181 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wrclock 1 CLK PIN_28 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 42; CLK Node = 'wrclock'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 624 320 488 640 "wrclock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.722 ns) 3.181 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_datain_reg0 2 MEM M4K_X19_Y5 1 " "Info: 2: + IC(0.990 ns) + CELL(0.722 ns) = 3.181 ns; Loc. = M4K_X19_Y5; Fanout = 1; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~porta_datain_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.712 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 68.88 % ) " "Info: Total cell delay = 2.191 ns ( 68.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.12 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.181 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.181 ns" { wrclock wrclock~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.167 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.167 ns" { wrclock wrclock~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.708ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.181 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.181 ns" { wrclock wrclock~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.167 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.167 ns" { wrclock wrclock~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_memory_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.708ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.181 ns" { wrclock ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.181 ns" { wrclock wrclock~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~porta_datain_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "square:inst2\|altsyncram:altsyncram_component\|altsyncram_b431:auto_generated\|ram_block1a4~porta_address_reg4 phasein\[4\] clk 9.596 ns memory " "Info: tsu for memory \"square:inst2\|altsyncram:altsyncram_component\|altsyncram_b431:auto_generated\|ram_block1a4~porta_address_reg4\" (data pin = \"phasein\[4\]\", clock pin = \"clk\") is 9.596 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.760 ns + Longest pin memory " "Info: + Longest pin to memory delay is 12.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns phasein\[4\] 1 PIN PIN_200 38 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_200; Fanout = 38; PIN Node = 'phasein\[4\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { phasein[4] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 88 344 512 104 "phasein\[11..0\]" "" } { 576 536 696 592 "phasein\[11..3\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(10.902 ns) + CELL(0.383 ns) 12.760 ns square:inst2\|altsyncram:altsyncram_component\|altsyncram_b431:auto_generated\|ram_block1a4~porta_address_reg4 2 MEM M4K_X19_Y23 1 " "Info: 2: + IC(10.902 ns) + CELL(0.383 ns) = 12.760 ns; Loc. = M4K_X19_Y23; Fanout = 1; MEM Node = 'square:inst2\|altsyncram:altsyncram_component\|altsyncram_b431:auto_generated\|ram_block1a4~porta_address_reg4'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.285 ns" { phasein[4] square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_b431.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_b431.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.858 ns ( 14.56 % ) " "Info: Total cell delay = 1.858 ns ( 14.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.902 ns ( 85.44 % ) " "Info: Total interconnect delay = 10.902 ns ( 85.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.760 ns" { phasein[4] square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "12.760 ns" { phasein[4] phasein[4]~out0 square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 10.902ns } { 0.000ns 1.475ns 0.383ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_b431.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_b431.tdf" 123 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.257 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to destination memory is 3.257 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 572 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 572; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 200 344 512 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.722 ns) 3.257 ns square:inst2\|altsyncram:altsyncram_component\|altsyncram_b431:auto_generated\|ram_block1a4~porta_address_reg4 2 MEM M4K_X19_Y23 1 " "Info: 2: + IC(1.066 ns) + CELL(0.722 ns) = 3.257 ns; Loc. = M4K_X19_Y23; Fanout = 1; MEM Node = 'square:inst2\|altsyncram:altsyncram_component\|altsyncram_b431:auto_generated\|ram_block1a4~porta_address_reg4'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.788 ns" { clk square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_b431.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_b431.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 67.27 % ) " "Info: Total cell delay = 2.191 ns ( 67.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.73 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.257 ns" { clk square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.257 ns" { clk clk~out0 square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.760 ns" { phasein[4] square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "12.760 ns" { phasein[4] phasein[4]~out0 square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 10.902ns } { 0.000ns 1.475ns 0.383ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.257 ns" { clk square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.257 ns" { clk clk~out0 square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk output\[8\] ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[8\] 14.510 ns memory " "Info: tco from clock \"clk\" to destination pin \"output\[8\]\" through memory \"ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[8\]\" is 14.510 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.162 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 3.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 572 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 572; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 200 344 512 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.703 ns) 3.162 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[8\] 2 MEM M4K_X19_Y5 1 " "Info: 2: + IC(0.990 ns) + CELL(0.703 ns) = 3.162 ns; Loc. = M4K_X19_Y5; Fanout = 1; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[8\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.693 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns ( 68.69 % ) " "Info: Total cell delay = 2.172 ns ( 68.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.31 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.162 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.162 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.703ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.698 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[8\] 1 MEM M4K_X19_Y5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X19_Y5; Fanout = 1; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[8\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.939 ns) + CELL(0.114 ns) 3.157 ns mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[8\]~534 2 COMB LC_X32_Y11_N2 1 " "Info: 2: + IC(2.939 ns) + CELL(0.114 ns) = 3.157 ns; Loc. = LC_X32_Y11_N2; Fanout = 1; COMB Node = 'mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[8\]~534'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.053 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~534 } "NODE_NAME" } } { "db/mux_ogc.tdf" "" { Text "F:/fpga test/dds/db/mux_ogc.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.818 ns) + CELL(0.114 ns) 5.089 ns mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[8\]~535 3 COMB LC_X21_Y11_N9 1 " "Info: 3: + IC(1.818 ns) + CELL(0.114 ns) = 5.089 ns; Loc. = LC_X21_Y11_N9; Fanout = 1; COMB Node = 'mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\|result_node\[8\]~535'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.932 ns" { mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~534 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~535 } "NODE_NAME" } } { "db/mux_ogc.tdf" "" { Text "F:/fpga test/dds/db/mux_ogc.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.485 ns) + CELL(2.124 ns) 10.698 ns output\[8\] 4 PIN PIN_41 0 " "Info: 4: + IC(3.485 ns) + CELL(2.124 ns) = 10.698 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'output\[8\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.609 ns" { mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~535 output[8] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 304 1160 1336 320 "output\[11..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.456 ns ( 22.96 % ) " "Info: Total cell delay = 2.456 ns ( 22.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.242 ns ( 77.04 % ) " "Info: Total interconnect delay = 8.242 ns ( 77.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.698 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~534 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~535 output[8] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "10.698 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~534 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~535 output[8] } { 0.000ns 2.939ns 1.818ns 3.485ns } { 0.104ns 0.114ns 0.114ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.162 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.162 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.703ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.698 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~534 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~535 output[8] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "10.698 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8] mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~534 mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated|result_node[8]~535 output[8] } { 0.000ns 2.939ns 1.818ns 3.485ns } { 0.104ns 0.114ns 0.114ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}