dds.tan.qmsg

verilog编写基于fpga的DDS实现

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 200 344 512 216 "clk" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wrclock " "Info: Assuming node \"wrclock\" is an undefined clock" {  } { { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 624 320 488 640 "wrclock" "" } } } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "wrclock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~portb_address_reg0 memory ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[11\] 196.97 MHz 5.077 ns Internal " "Info: Clock \"clk\" has Internal fmax of 196.97 MHz between source memory \"ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~portb_address_reg0\" and destination memory \"ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[11\]\" (period= 5.077 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~portb_address_reg0 1 MEM M4K_X19_Y5 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y5; Fanout = 9; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~portb_address_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[11\] 2 MEM M4K_X19_Y5 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X19_Y5; Fanout = 1; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[11\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.015 ns - Smallest " "Info: - Smallest clock skew is -0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.162 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 3.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 572 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 572; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 200 344 512 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.703 ns) 3.162 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[11\] 2 MEM M4K_X19_Y5 1 " "Info: 2: + IC(0.990 ns) + CELL(0.703 ns) = 3.162 ns; Loc. = M4K_X19_Y5; Fanout = 1; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|q_b\[11\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.693 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns ( 68.69 % ) " "Info: Total cell delay = 2.172 ns ( 68.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.31 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.162 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.162 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.703ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.177 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 3.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 572 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 572; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "F:/fpga test/dds/dds.bdf" { { 200 344 512 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.718 ns) 3.177 ns ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~portb_address_reg0 2 MEM M4K_X19_Y5 9 " "Info: 2: + IC(0.990 ns) + CELL(0.718 ns) = 3.177 ns; Loc. = M4K_X19_Y5; Fanout = 9; MEM Node = 'ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\|ram_block1a11~portb_address_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.708 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns ( 68.84 % ) " "Info: Total cell delay = 2.187 ns ( 68.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.16 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.177 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.177 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.718ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.162 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.162 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.703ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.177 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.177 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.718ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 400 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_vpl1.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.162 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.162 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.703ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.177 ns" { clk ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.177 ns" { clk clk~out0 ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.718ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|hub_tdo 115.21 MHz 8.68 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 115.21 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 8.68 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.079 ns + Longest register register " "Info: + Longest register to register delay is 4.079 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LC_X27_Y14_N9 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y14_N9; Fanout = 24; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.570 ns) + CELL(0.590 ns) 1.160 ns cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|no_name_gen~33 2 COMB LC_X27_Y14_N8 7 " "Info: 2: + IC(0.570 ns) + CELL(0.590 ns) = 1.160 ns; Loc. = LC_X27_Y14_N8; Fanout = 7; COMB Node = 'cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|no_name_gen~33'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.160 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~33 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.305 ns) + CELL(0.442 ns) 2.907 ns sld_hub:sld_hub_inst\|hub_tdo~982 3 COMB LC_X28_Y13_N2 1 " "Info: 3: + IC(1.305 ns) + CELL(0.442 ns) = 2.907 ns; Loc. = LC_X28_Y13_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~982'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.747 ns" { cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~33 sld_hub:sld_hub_inst|hub_tdo~982 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.738 ns) 4.079 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X28_Y13_N6 1 " "Info: 4: + IC(0.434 ns) + CELL(0.738 ns) = 4.079 ns; Loc. = LC_X28_Y13_N6; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.172 ns" { sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.770 ns ( 43.39 % ) " "Info: Total cell delay = 1.770 ns ( 43.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.309 ns ( 56.61 % ) " "Info: Total interconnect delay = 2.309 ns ( 56.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.079 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~33 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.079 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~33 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.570ns 1.305ns 0.434ns } { 0.000ns 0.590ns 0.442ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.355 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 526 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 526; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.644 ns) + CELL(0.711 ns) 5.355 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X28_Y13_N6 1 " "Info: 2: + IC(4.644 ns) + CELL(0.711 ns) = 5.355 ns; Loc. = LC_X28_Y13_N6; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.28 % ) " "Info: Total cell delay = 0.711 ns ( 13.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.644 ns ( 86.72 % ) " "Info: Total interconnect delay = 4.644 ns ( 86.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.644ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.355 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 526 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 526; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.644 ns) + CELL(0.711 ns) 5.355 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 2 REG LC_X27_Y14_N9 24 " "Info: 2: + IC(4.644 ns) + CELL(0.711 ns) = 5.355 ns; Loc. = LC_X27_Y14_N9; Fanout = 24; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.28 % ) " "Info: Total cell delay = 0.711 ns ( 13.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.644 ns ( 86.72 % ) " "Info: Total interconnect delay = 4.644 ns ( 86.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.644ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.644ns } { 0.000ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.644ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.079 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~33 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.079 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~33 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.570ns 1.305ns 0.434ns } { 0.000ns 0.590ns 0.442ns 0.738ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.644ns } { 0.000ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.644ns } { 0.000ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}