dds.fit.qmsg

verilog编写基于fpga的DDS实现

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.461 ns memory register " "Info: Estimated most critical path is memory to register delay of 6.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|altsyncram_4pi2:altsyncram1\|ram_block3a10~portb_address_reg11 1 MEM M4K_X33_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y8; Fanout = 1; MEM Node = 'cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|altsyncram_4pi2:altsyncram1\|ram_block3a10~portb_address_reg11'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|altsyncram_4pi2:altsyncram1|ram_block3a10~portb_address_reg11 } "NODE_NAME" } } { "db/altsyncram_4pi2.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_4pi2.tdf" 388 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|altsyncram_4pi2:altsyncram1\|q_b\[10\] 2 MEM M4K_X33_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y8; Fanout = 1; MEM Node = 'cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|altsyncram_4pi2:altsyncram1\|q_b\[10\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.317 ns" { cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|altsyncram_4pi2:altsyncram1|ram_block3a10~portb_address_reg11 cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|altsyncram_4pi2:altsyncram1|q_b[10] } "NODE_NAME" } } { "db/altsyncram_4pi2.tdf" "" { Text "F:/fpga test/dds/db/altsyncram_4pi2.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.738 ns) 6.461 ns cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[10\] 3 REG LAB_X25_Y11 2 " "Info: 3: + IC(1.406 ns) + CELL(0.738 ns) = 6.461 ns; Loc. = LAB_X25_Y11; Fanout = 2; REG Node = 'cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[10\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.144 ns" { cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|altsyncram_4pi2:altsyncram1|q_b[10] cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[10] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 413 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.055 ns ( 78.24 % ) " "Info: Total cell delay = 5.055 ns ( 78.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.406 ns ( 21.76 % ) " "Info: Total interconnect delay = 1.406 ns ( 21.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/q