dds.fit.qmsg

verilog编写基于fpga的DDS实现

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~980 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~980\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~981 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~981\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination \"cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~983 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~983\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~984 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~984\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_3u41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_3u41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } { { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_3u41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination \"sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_3u41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "F:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 Global clock " "Info: Automatically promoted signal \"cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" to use Global clock" {  } { { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ut41:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}