📄 dds.tan.rpt
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; altera_internal_jtag~TCKUTAP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; wrclock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg1 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg2 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg3 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg4 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg5 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg6 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg7 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg8 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[11] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg1 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg2 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg3 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg4 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg5 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg6 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg7 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg8 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[1] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg0 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg1 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg2 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg3 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg4 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg5 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg6 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
; N/A ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a11~portb_address_reg7 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[3] ; clk ; clk ; None ; None ; 4.319 ns ;
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