dds.tan.rpt

verilog编写基于fpga的DDS实现

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                      ; To                                                                                                          ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 9.596 ns                         ; phasein[4]                                                                                                ; square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4 ; --                           ; clk                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 14.510 ns                        ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8]                           ; output[8]                                                                                                   ; clk                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 18.155 ns                        ; select[0]                                                                                                 ; output[3]                                                                                                   ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.616 ns                         ; altera_internal_jtag~TMSUTAP                                                                              ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]                                    ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 115.21 MHz ( period = 8.680 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                 ; sld_hub:sld_hub_inst|hub_tdo                                                                                ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 196.97 MHz ( period = 5.077 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a10~portb_address_reg8 ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[2]                             ; clk                          ; clk                          ; 0            ;
; Clock Setup: 'wrclock'                      ; N/A   ; None          ; 197.01 MHz ( period = 5.076 ns ) ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a10~porta_datain_reg2  ; ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a10~porta_memory_reg2    ; wrclock                      ; wrclock                      ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                           ;                                                                                                             ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+