dds.map.summary

来自「verilog编写基于fpga的DDS实现」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Tue Jul 10 16:41:32 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Total logic elements : 275
Total pins : 59
Total virtual pins : 0
Total memory bits : 153,600
Total PLLs : 0