dds.tan.summary

来自「verilog编写基于fpga的DDS实现」· SUMMARY 代码 · 共 87 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.596 ns
From           : phasein[4]
To             : square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated|ram_block1a4~porta_address_reg4
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.510 ns
From           : ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[8]
To             : output[8]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 18.155 ns
From           : select[0]
To             : output[3]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.616 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 115.21 MHz ( period = 8.680 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 196.97 MHz ( period = 5.077 ns )
From           : ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a10~portb_address_reg8
To             : ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|q_b[2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'wrclock'
Slack          : N/A
Required Time  : None
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a10~porta_datain_reg2
To             : ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated|ram_block1a10~porta_memory_reg2
From Clock     : wrclock
To Clock       : wrclock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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