dds_lut.bsf

verilog编写基于fpga的DDS实现

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 232 208)
	(text "dds_lut" (rect 5 0 46 14)(font "Arial" (font_size 8)))
	(text "inst" (rect 8 176 25 188)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "phasein[11..0]" (rect 0 0 80 14)(font "Arial" (font_size 8)))
		(text "phasein[11..0]" (rect 21 27 101 41)(font "Arial" (font_size 8)))
		(line (pt 0 32)(pt 16 32)(line_width 3))
	)
	(port
		(pt 0 48)
		(input)
		(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
		(text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8)))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "select[1..0]" (rect 0 0 62 14)(font "Arial" (font_size 8)))
		(text "select[1..0]" (rect 21 59 83 73)(font "Arial" (font_size 8)))
		(line (pt 0 64)(pt 16 64)(line_width 3))
	)
	(port
		(pt 0 80)
		(input)
		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
		(text "data[15..0]" (rect 21 75 81 89)(font "Arial" (font_size 8)))
		(line (pt 0 80)(pt 16 80)(line_width 3))
	)
	(port
		(pt 0 96)
		(input)
		(text "wraddress[8..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
		(text "wraddress[8..0]" (rect 21 91 113 105)(font "Arial" (font_size 8)))
		(line (pt 0 96)(pt 16 96)(line_width 3))
	)
	(port
		(pt 0 112)
		(input)
		(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
		(text "wren" (rect 21 107 51 121)(font "Arial" (font_size 8)))
		(line (pt 0 112)(pt 16 112)(line_width 1))
	)
	(port
		(pt 0 128)
		(input)
		(text "rden" (rect 0 0 25 14)(font "Arial" (font_size 8)))
		(text "rden" (rect 21 123 46 137)(font "Arial" (font_size 8)))
		(line (pt 0 128)(pt 16 128)(line_width 1))
	)
	(port
		(pt 0 144)
		(input)
		(text "wrclock" (rect 0 0 46 14)(font "Arial" (font_size 8)))
		(text "wrclock" (rect 21 139 67 153)(font "Arial" (font_size 8)))
		(line (pt 0 144)(pt 16 144)(line_width 1))
	)
	(port
		(pt 216 32)
		(output)
		(text "output[11..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
		(text "output[11..0]" (rect 125 27 195 41)(font "Arial" (font_size 8)))
		(line (pt 216 32)(pt 200 32)(line_width 3))
	)
	(drawing
		(rectangle (rect 16 16 200 176)(line_width 1))
	)
)