dds.fit.summary

来自「verilog编写基于fpga的DDS实现」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Tue Jul 10 16:40:36 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Total logic elements : 272 / 12,060 ( 2 % )
Total pins : 59 / 173 ( 34 % )
Total virtual pins : 0
Total memory bits : 153,600 / 239,616 ( 64 % )
Total PLLs : 0 / 2 ( 0 % )