dds.map.rpt

verilog编写基于fpga的DDS实现

Analysis & Synthesis report for dds
Tue Jul 10 16:41:32 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for ram:inst7|altsyncram:altsyncram_component|altsyncram_vpl1:auto_generated
 12. Source assignments for square:inst2|altsyncram:altsyncram_component|altsyncram_b431:auto_generated
 13. Source assignments for cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|altsyncram_4pi2:altsyncram1
 14. Source assignments for cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
 15. Source assignments for sin_rom:inst|altsyncram:altsyncram_component|altsyncram_3u41:auto_generated|altsyncram_9pi2:altsyncram1
 16. Source assignments for sin_rom:inst|altsyncram:altsyncram_component|altsyncram_3u41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
 17. Source assignments for sld_hub:sld_hub_inst
 18. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 19. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 20. Parameter Settings for User Entity Instance: mux4:inst3|lpm_mux:lpm_mux_component
 21. Parameter Settings for User Entity Instance: ram:inst7|altsyncram:altsyncram_component
 22. Parameter Settings for User Entity Instance: square:inst2|altsyncram:altsyncram_component
 23. Parameter Settings for User Entity Instance: cos_rom:inst1|altsyncram:altsyncram_component
 24. Parameter Settings for User Entity Instance: cos_rom:inst1|altsyncram:altsyncram_component|altsyncram_ut41:auto_generated|sld_mod_ram_rom:mgl_prim2
 25. Parameter Settings for User Entity Instance: sin_rom:inst|altsyncram:altsyncram_component
 26. Parameter Settings for User Entity Instance: sin_rom:inst|altsyncram:altsyncram_component|altsyncram_3u41:auto_generated|sld_mod_ram_rom:mgl_prim2
 27. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 28. In-System Memory Content Editor Settings
 29. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jul 10 16:41:32 2007    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; dds                                      ;
; Top-level Entity Name       ; dds                                      ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 275                                      ;
; Total pins                  ; 59                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 153,600                                  ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1C12Q240C8       ;                    ;
; Top-level entity name                                              ; dds                ; dds                ;
; Family name                                                        ; Cyclone            ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;