cpld-0809.vhd

VHDL语言编写的关于ADC0809的程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity adc is
  port(d:in std_logic_vector(7 downto 0);			
       clk,eoc:in std_logic;
       wr,cs,rd:out std_logic;
       adda:out std_logic_vector(7 downto 0);
       c_state:out std_logic_vector(3 downto 0);
       q:out std_logic_vector(7 downto 0);
       outbit:out std_logic_vector(7 downto 0);   
	   oe1,oe2,oe3,oe4,dir1,dir2,dir3,dir4:out std_logic);
end adc;

architecture behav of adc is
signal current_state,next_state:std_logic_vector(3 downto 0);  
signal fp:std_logic_vector(15 downto 0);
signal f:std_logic; 
signal display:std_logic_vector(7 downto 0);
signal rdoutbit:std_logic;--_vector(7 downto 0);
 constant st0:std_logic_vector(3 downto 0):="0111";	--no	
 constant st1:std_logic_vector(3 downto 0):="0001";  --start
 constant st2:std_logic_vector(3 downto 0):="1111";  --wait
 constant st3:std_logic_vector(3 downto 0):="0010";  --read
 
begin
 adda<="00000000";
cs<=current_state(2);wr<=current_state(1);
 rd<=current_state(0);c_state<=current_state;

com:process(current_state,eoc) begin
case current_state is
 when st0=>next_state<=st1;
 when st1=>next_state<=st2;
 when st2=>if(eoc='0') then next_state<=st3;

		case rdoutbit is
    		when '0'=>outbit<="11111110";
				display<=d and "00001111";
					case display is
 						when "00000000"=>q<="01111110"; --0
					    when "00000001"=>q<="00001100"; --1
 						when "00000010"=>q<="10110110"; --2
 						when "00000011"=>q<="10011110"; --3
 						when "00000100"=>q<="11001100"; --4
 						when "00000101"=>q<="11011010"; --5
 						when "00000110"=>q<="11111010"; --6
 						when "00000111"=>q<="00001110"; --7
 						when "00001000"=>q<="11111110"; --8
 						when "00001001"=>q<="11011110"; --9
					    when "00001010"=>q<="11101110"; --A
 						when "00001011"=>q<="11111000"; --B
 						when "00001100"=>q<="01110010"; --C
 						when "00001101"=>q<="10111100"; --D
 						when "00001110"=>q<="11110010"; --E
 						when "00001111"=>q<="11100010"; --F
 						when others =>q<="ZZZZZZZZ";
					end case;
    		when '1'=>outbit<="11111101";
                display<=d and "11110000";
					case display is
 						when "00000000"=>q<="01111110"; --0
					    when "00010000"=>q<="00001100"; --1
 						when "00100000"=>q<="10110110"; --2
 						when "00110000"=>q<="10011110"; --3
 						when "01000000"=>q<="11001100"; --4
 						when "01010000"=>q<="11011010"; --5
 						when "01100000"=>q<="11111010"; --6
 						when "01110000"=>q<="00001110"; --7
 						when "10000000"=>q<="11111110"; --8
 						when "10010000"=>q<="11011110"; --9
					    when "10100000"=>q<="11101110"; --A
 						when "10110000"=>q<="11111000"; --B
 						when "11000000"=>q<="01110010"; --C
 						when "11010000"=>q<="10111100"; --D
 						when "11100000"=>q<="11110010"; --E
 						when "11110000"=>q<="11100010"; --F
 						when others =>q<="ZZZZZZZZ";
					end case;
    	    when others=>outbit<="ZZZZZZZZ";
       end case; 
else next_state<=st2;
end if;
when st3=>next_state<=st0;
when others=>next_state<=st0;
end case;
end process com;

rega:process(clk)
	begin
	if (clk'event and clk='1') then
	if fp=50 then
	  fp<="0000000000000000";
      f<=not f;       
	else
		fp<=fp+1;
		rdoutbit<=not rdoutbit;
	end if;
  end if;
end process rega;

reg:process(f)
 begin
  if (f'event and f='1') then current_state<=next_state;
 end if;  
end process reg;


 oe1<='0';
 dir1<='1';
 oe2<='0';
 dir2<='0';

 oe3<='0';
 dir3<='1';
 oe4<='0';
 dir4<='1';

end behav;