clock_my.tan.qmsg

实光电码盘的输出数据的四倍频

{ "Info" "ITDB_TSU_RESULT" "SENSOR_AB\[0\] SENSOR_B CLK 11.000 ns register " "Info: tsu for register \"SENSOR_AB\[0\]\" (data pin = \"SENSOR_B\", clock pin = \"CLK\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SENSOR_B 1 PIN PIN_51 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 'SENSOR_B'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { SENSOR_B } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns SENSOR_AB\[0\] 2 REG LC54 98 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC54; Fanout = 98; REG Node = 'SENSOR_AB\[0\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "8.000 ns" { SENSOR_B SENSOR_AB[0] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "10.000 ns" { SENSOR_B SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { SENSOR_B SENSOR_B~out SENSOR_AB[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 20 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 20; CLK Node = 'CLK'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { CLK } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SENSOR_AB\[0\] 2 REG LC54 98 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC54; Fanout = 98; REG Node = 'SENSOR_AB\[0\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "0.000 ns" { CLK SENSOR_AB[0] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SENSOR_AB[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "10.000 ns" { SENSOR_B SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { SENSOR_B SENSOR_B~out SENSOR_AB[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SENSOR_AB[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DATA_OUT\[7\] COUNTER\[7\] 26.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"DATA_OUT\[7\]\" through register \"COUNTER\[7\]\" is 26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 20 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 20; CLK Node = 'CLK'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { CLK } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns COUNTER\[7\] 2 REG LC40 56 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC40; Fanout = 56; REG Node = 'COUNTER\[7\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "0.000 ns" { CLK COUNTER[7] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK COUNTER[7] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out COUNTER[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns + Longest register pin " "Info: + Longest register to pin delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNTER\[7\] 1 REG LC40 56 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC40; Fanout = 56; REG Node = 'COUNTER\[7\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { COUNTER[7] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns DATA_OUT~71 2 COMB LC8 3 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC8; Fanout = 3; COMB Node = 'DATA_OUT~71'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "9.000 ns" { COUNTER[7] DATA_OUT~71 } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 18.000 ns DATA_OUT\[7\]\$latch~10 3 COMB LOOP LC115 3 " "Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 18.000 ns; Loc. = LC115; Fanout = 3; COMB LOOP Node = 'DATA_OUT\[7\]\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "DATA_OUT\[7\]\$latch~10 LC115 " "Info: Loc. = LC115; Node \"DATA_OUT\[7\]\$latch~10\"" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { DATA_OUT[7]$latch~10 } "NODE_NAME" } "" } }  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { DATA_OUT[7]$latch~10 } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "9.000 ns" { DATA_OUT~71 DATA_OUT[7]$latch~10 } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 22.000 ns DATA_OUT\[7\] 4 PIN PIN_73 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 22.000 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'DATA_OUT\[7\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "4.000 ns" { DATA_OUT[7]$latch~10 DATA_OUT[7] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.000 ns 90.91 % " "Info: Total cell delay = 20.000 ns ( 90.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 9.09 % " "Info: Total interconnect delay = 2.000 ns ( 9.09 % )" {  } {  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "22.000 ns" { COUNTER[7] DATA_OUT~71 DATA_OUT[7]$latch~10 DATA_OUT[7] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "22.000 ns" { COUNTER[7] DATA_OUT~71 DATA_OUT[7]$latch~10 DATA_OUT[7] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 7.000ns 9.000ns 4.000ns } } }  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK COUNTER[7] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out COUNTER[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "22.000 ns" { COUNTER[7] DATA_OUT~71 DATA_OUT[7]$latch~10 DATA_OUT[7] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "22.000 ns" { COUNTER[7] DATA_OUT~71 DATA_OUT[7]$latch~10 DATA_OUT[7] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 7.000ns 9.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "READ_ADD DATA_OUT\[7\] 24.000 ns Longest " "Info: Longest tpd from source pin \"READ_ADD\" to destination pin \"DATA_OUT\[7\]\" is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns READ_ADD 1 PIN PIN_54 16 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 16; PIN Node = 'READ_ADD'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { READ_ADD } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns DATA_OUT~71 2 COMB LC8 3 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC8; Fanout = 3; COMB Node = 'DATA_OUT~71'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "9.000 ns" { READ_ADD DATA_OUT~71 } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 20.000 ns DATA_OUT\[7\]\$latch~10 3 COMB LOOP LC115 3 " "Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 20.000 ns; Loc. = LC115; Fanout = 3; COMB LOOP Node = 'DATA_OUT\[7\]\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "DATA_OUT\[7\]\$latch~10 LC115 " "Info: Loc. = LC115; Node \"DATA_OUT\[7\]\$latch~10\"" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { DATA_OUT[7]$latch~10 } "NODE_NAME" } "" } }  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { DATA_OUT[7]$latch~10 } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "9.000 ns" { DATA_OUT~71 DATA_OUT[7]$latch~10 } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 24.000 ns DATA_OUT\[7\] 4 PIN PIN_73 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 24.000 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'DATA_OUT\[7\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "4.000 ns" { DATA_OUT[7]$latch~10 DATA_OUT[7] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "22.000 ns 91.67 % " "Info: Total cell delay = 22.000 ns ( 91.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.33 % " "Info: Total interconnect delay = 2.000 ns ( 8.33 % )" {  } {  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "24.000 ns" { READ_ADD DATA_OUT~71 DATA_OUT[7]$latch~10 DATA_OUT[7] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "24.000 ns" { READ_ADD READ_ADD~out DATA_OUT~71 DATA_OUT[7]$latch~10 DATA_OUT[7] } { 0.000ns 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 7.000ns 9.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "SENSOR_AB\[0\] SENSOR_B CLK -3.000 ns register " "Info: th for register \"SENSOR_AB\[0\]\" (data pin = \"SENSOR_B\", clock pin = \"CLK\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 20 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 20; CLK Node = 'CLK'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { CLK } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SENSOR_AB\[0\] 2 REG LC54 98 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC54; Fanout = 98; REG Node = 'SENSOR_AB\[0\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "0.000 ns" { CLK SENSOR_AB[0] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SENSOR_AB[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SENSOR_B 1 PIN PIN_51 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 'SENSOR_B'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { SENSOR_B } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns SENSOR_AB\[0\] 2 REG LC54 98 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC54; Fanout = 98; REG Node = 'SENSOR_AB\[0\]'" {  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "8.000 ns" { SENSOR_B SENSOR_AB[0] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "10.000 ns" { SENSOR_B SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { SENSOR_B SENSOR_B~out SENSOR_AB[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SENSOR_AB[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "10.000 ns" { SENSOR_B SENSOR_AB[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { SENSOR_B SENSOR_B~out SENSOR_AB[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 13 10:02:39 2006 " "Info: Processing ended: Tue Jun 13 10:02:39 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}