📄 clock_my.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DATA_OUT\[4\]\$latch~10 " "Info: Node \"DATA_OUT\[4\]\$latch~10\"" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0} } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DATA_OUT\[3\]\$latch~10 " "Info: Node \"DATA_OUT\[3\]\$latch~10\"" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0} } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DATA_OUT\[2\]\$latch~10 " "Info: Node \"DATA_OUT\[2\]\$latch~10\"" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0} } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DATA_OUT\[1\]\$latch~10 " "Info: Node \"DATA_OUT\[1\]\$latch~10\"" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0} } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DATA_OUT\[0\]\$latch~10 " "Info: Node \"DATA_OUT\[0\]\$latch~10\"" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0} } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 32 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "process0_175~10 " "Info: Node \"process0_175~10\"" { } { } 0} } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 7 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register SENSOR_AB\[1\] register COUNTER\[15\] 41.67 MHz 24.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 41.67 MHz between source register \"SENSOR_AB\[1\]\" and destination register \"COUNTER\[15\]\" (period= 24.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.000 ns + Longest register register " "Info: + Longest register to register delay is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SENSOR_AB\[1\] 1 REG LC55 146 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC55; Fanout = 146; REG Node = 'SENSOR_AB\[1\]'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { SENSOR_AB[1] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns Mux~8068 2 COMB LC57 60 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC57; Fanout = 60; COMB Node = 'Mux~8068'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "9.000 ns" { SENSOR_AB[1] Mux~8068 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 17.000 ns Mux~8252 3 COMB LC23 1 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 17.000 ns; Loc. = LC23; Fanout = 1; COMB Node = 'Mux~8252'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "8.000 ns" { Mux~8068 Mux~8252 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 18.000 ns Mux~8254 4 COMB LC24 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 18.000 ns; Loc. = LC24; Fanout = 1; COMB Node = 'Mux~8254'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "1.000 ns" { Mux~8252 Mux~8254 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 19.000 ns COUNTER\[15\] 5 REG LC25 5 " "Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 19.000 ns; Loc. = LC25; Fanout = 5; REG Node = 'COUNTER\[15\]'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "1.000 ns" { Mux~8254 COUNTER[15] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns 78.95 % " "Info: Total cell delay = 15.000 ns ( 78.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 21.05 % " "Info: Total interconnect delay = 4.000 ns ( 21.05 % )" { } { } 0} } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "19.000 ns" { SENSOR_AB[1] Mux~8068 Mux~8252 Mux~8254 COUNTER[15] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "19.000 ns" { SENSOR_AB[1] Mux~8068 Mux~8252 Mux~8254 COUNTER[15] } { 0.000ns 2.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 7.000ns 6.000ns 1.000ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 20 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 20; CLK Node = 'CLK'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { CLK } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns COUNTER\[15\] 2 REG LC25 5 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC25; Fanout = 5; REG Node = 'COUNTER\[15\]'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "0.000 ns" { CLK COUNTER[15] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK COUNTER[15] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out COUNTER[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 20 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 20; CLK Node = 'CLK'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "" { CLK } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SENSOR_AB\[1\] 2 REG LC55 146 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC55; Fanout = 146; REG Node = 'SENSOR_AB\[1\]'" { } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "0.000 ns" { CLK SENSOR_AB[1] } "NODE_NAME" } "" } } { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK SENSOR_AB[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SENSOR_AB[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK COUNTER[15] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out COUNTER[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK SENSOR_AB[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SENSOR_AB[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 -1 0 } } } 0} } { { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "19.000 ns" { SENSOR_AB[1] Mux~8068 Mux~8252 Mux~8254 COUNTER[15] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "19.000 ns" { SENSOR_AB[1] Mux~8068 Mux~8252 Mux~8254 COUNTER[15] } { 0.000ns 2.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 7.000ns 6.000ns 1.000ns 1.000ns } } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK COUNTER[15] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out COUNTER[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" "" { Report "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY_cmp.qrpt" Compiler "CLOCK_MY" "UNKNOWN" "V1" "E:/altera/quartus42/my_vhdl/zhuangtai/db/CLOCK_MY.quartus_db" { Floorplan "E:/altera/quartus42/my_vhdl/zhuangtai/" "" "3.000 ns" { CLK SENSOR_AB[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out SENSOR_AB[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0}
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