clock_my222.vhd

实光电码盘的输出数据的四倍频

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY CLOCK_MY IS 
	PORT( 	  	 CLK  : IN  STD_LOGIC;			--CPLD系统时钟	 	
			 SENSOR_A : IN  STD_LOGIC;			--码盘A信号
			 SENSOR_B : IN  STD_LOGIC;			--码盘B信号
			      CLR : IN  STD_LOGIC;			--计数器清零信号
			
		     DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
		 );
END CLOCK_MY;



ARCHITECTURE CLOCK_MY_1 OF CLOCK_MY IS

 	SIGNAL      COUNTER :  STD_LOGIC_VECTOR(31 DOWNTO 0);  	  --32位计数器
	SIGNAL  SENSOR_AB   :  STD_LOGIC_VECTOR(3 DOWNTO 0);	  --码盘状态:
															  --第四位上一次SENSOR_A
															  --第三位上一次SENSOR_B
															  --第二位现在SENSOR_A
															  --第一位现在SENSOR_B
BEGIN

	PROCESS (CLK,CLR)	
	BEGIN	
		IF   CLR = '0'  THEN  
		      COUNTER   <= (OTHERS=>'0');
			  SENSOR_AB <= (OTHERS=>'0');
		
	  	ELSIF CLK'EVENT AND ( CLK = '1' ) AND ( CLK'LAST_VALUE = '0' ) THEN
	          SENSOR_AB(3 DOWNTO 2) <= SENSOR_AB(1 DOWNTO 0);
	          SENSOR_AB(1) <= SENSOR_A;
			  SENSOR_AB(0) <= SENSOR_B;        					  
			  CASE  SENSOR_AB IS 
					WHEN  "0001"  => COUNTER <= COUNTER - 1;
					WHEN  "0111"  => COUNTER <= COUNTER - 1;
					WHEN  "1110"  => COUNTER <= COUNTER - 1;
					WHEN  "1000"  => COUNTER <= COUNTER - 1;					
					WHEN  "0010"  => COUNTER <= COUNTER + 1;
					WHEN  "1011"  => COUNTER <= COUNTER + 1;
					WHEN  "1101"  => COUNTER <= COUNTER + 1;
					WHEN  "0100"  => COUNTER <= COUNTER + 1;					
					WHEN  OTHERS  => COUNTER <= COUNTER;
              END CASE;	 		  
	  	END IF;		
	END PROCESS; 
	
	DATA_OUT( 7 DOWNTO 0 ) <= COUNTER( 7 DOWNTO 0 );		

END ARCHITECTURE CLOCK_MY_1;