clock_my.tan.rpt

实光电码盘的输出数据的四倍频

; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[7] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[7] ;
; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[6] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[6] ;
; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[5] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[5] ;
; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[4] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[4] ;
; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[3] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[3] ;
; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[2] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[2] ;
; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[1] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[1] ;
; N/A   ; None              ; 22.000 ns       ; CLR      ; DATA_OUT[0] ;
; N/A   ; None              ; 22.000 ns       ; READ_OE  ; DATA_OUT[0] ;
+-------+-------------------+-----------------+----------+-------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+----------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To           ; To Clock ;
+---------------+-------------+-----------+----------+--------------+----------+
; N/A           ; None        ; -3.000 ns ; SENSOR_B ; SENSOR_AB[0] ; CLK      ;
; N/A           ; None        ; -3.000 ns ; SENSOR_A ; SENSOR_AB[1] ; CLK      ;
+---------------+-------------+-----------+----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Tue Jun 13 10:02:38 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off CLOCK_MY -c CLOCK_MY
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[7]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[6]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[5]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[4]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[3]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[2]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[1]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "DATA_OUT[0]$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "process0_175~10"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 41.67 MHz between source register "SENSOR_AB[1]" and destination register "COUNTER[15]" (period= 24.0 ns)
    Info: + Longest register to register delay is 19.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC55; Fanout = 146; REG Node = 'SENSOR_AB[1]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC57; Fanout = 60; COMB Node = 'Mux~8068'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 17.000 ns; Loc. = LC23; Fanout = 1; COMB Node = 'Mux~8252'
        Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 18.000 ns; Loc. = LC24; Fanout = 1; COMB Node = 'Mux~8254'
        Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 19.000 ns; Loc. = LC25; Fanout = 5; REG Node = 'COUNTER[15]'
        Info: Total cell delay = 15.000 ns ( 78.95 % )
        Info: Total interconnect delay = 4.000 ns ( 21.05 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 20; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC25; Fanout = 5; REG Node = 'COUNTER[15]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 20; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC55; Fanout = 146; REG Node = 'SENSOR_AB[1]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "SENSOR_AB[0]" (data pin = "SENSOR_B", clock pin = "CLK") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 'SENSOR_B'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC54; Fanout = 98; REG Node = 'SENSOR_AB[0]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "CLK" to