clock_my.map.rpt

实光电码盘的输出数据的四倍频

      |-- look_add:look_ahead_unit
      |-- altshift:oflow_ext_latency_ffs
      |-- altshift:result_ext_latency_ffs


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; DATA_OUT[7]$latch                             ;   ;
; process0_218                                  ;   ;
; DATA_OUT[6]$latch                             ;   ;
; DATA_OUT[5]$latch                             ;   ;
; DATA_OUT[4]$latch                             ;   ;
; DATA_OUT[3]$latch                             ;   ;
; DATA_OUT[2]$latch                             ;   ;
; DATA_OUT[1]$latch                             ;   ;
; DATA_OUT[0]$latch                             ;   ;
; Number of user-specified and inferred latches ; 9 ;
+-----------------------------------------------+---+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                               ;
+------------------------------------+------------+------+--------------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Macrocells ; Pins ; Full Hierarchy Name                                                      ;
+------------------------------------+------------+------+--------------------------------------------------------------------------+
; |CLOCK_MY                          ; 127        ; 15   ; |CLOCK_MY                                                                ;
;    |lpm_add_sub:add_rtl_0|         ; 20         ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0                                          ;
;       |addcore:adder[0]|           ; 1          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[0]                         ;
;          |a_csnbuffer:result_node| ; 1          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node ;
;       |addcore:adder[1]|           ; 4          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[1]                         ;
;          |a_csnbuffer:result_node| ; 4          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node ;
;       |addcore:adder[2]|           ; 8          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[2]                         ;
;          |a_csnbuffer:result_node| ; 8          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[2]|a_csnbuffer:result_node ;
;       |addcore:adder[3]|           ; 7          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[3]                         ;
;          |a_csnbuffer:result_node| ; 5          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_0|addcore:adder[3]|a_csnbuffer:result_node ;
;    |lpm_add_sub:add_rtl_1|         ; 19         ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1                                          ;
;       |addcore:adder[0]|           ; 1          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[0]                         ;
;          |a_csnbuffer:result_node| ; 1          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node ;
;       |addcore:adder[1]|           ; 4          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[1]                         ;
;          |a_csnbuffer:result_node| ; 4          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node ;
;       |addcore:adder[2]|           ; 8          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[2]                         ;
;          |a_csnbuffer:result_node| ; 8          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[2]|a_csnbuffer:result_node ;
;       |addcore:adder[3]|           ; 6          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[3]                         ;
;          |a_csnbuffer:result_node| ; 5          ; 0    ; |CLOCK_MY|lpm_add_sub:add_rtl_1|addcore:adder[3]|a_csnbuffer:result_node ;
+------------------------------------+------------+------+--------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; CLOCK_MY.vhd                     ; yes             ; E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd                  ;
; lpm_add_sub.tdf                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; e:/altera/quartus42/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; e:/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; e:/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal42.inc                    ; yes             ; e:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; addcore.tdf                      ; yes             ; e:/altera/quartus42/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf         ;
; look_add.tdf                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/look_add.tdf            ;
; altshift.tdf                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 127                  ;
; Total registers      ; 36                   ;
; I/O pins             ; 15                   ;
; Shareable expanders  ; 16                   ;
; Parallel expanders   ; 31                   ;
; Maximum fan-out node ; SENSOR_AB[1]         ;
; Maximum fan-out      ; 70                   ;
; Total fan-out        ; 1622                 ;
; Average fan-out      ; 10.27                ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Tue Jun 13 16:19:55 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off CLOCK_MY -c CLOCK_MY
Info: Found 2 design units, including 1 entities, in source file CLOCK_MY.vhd
    Info: Found design unit 1: CLOCK_MY-CLOCK_MY_1
    Info: Found entity 1: CLOCK_MY
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(36): signal "CLR" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(40): signal "READ_OE" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(41): signal "READ_ADD" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(42): signal "COUNTER" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(43): signal "READ_ADD" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(44): signal "COUNTER" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(45): signal "READ_ADD" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(46): signal "COUNTER" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(47): signal "READ_ADD" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(48): signal "COUNTER" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at CLOCK_MY.vhd(34): signal or variable "DATA_OUT" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "DATA_OUT" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 61 buffer(s)
    Info: Ignored 61 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Implemented 158 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 8 output pins
    Info: Implemented 127 macrocells
    Info: Implemented 16 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Processing ended: Tue Jun 13 16:20:30 2006
    Info: Elapsed time: 00:00:36