📄 time_disp_select.fit.rpt
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; clk_1khz ; PIN_43 ; 4 ; Clock ; yes ; On ; -- ;
; clk~24 ; LC13 ; 7 ; Clock ; no ; -- ; -- ;
+----------+----------+---------+-------+--------+----------------------+------------------+
+-------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+----------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+----------+----------+---------+----------------------+------------------+
; clk_1khz ; PIN_43 ; 4 ; On ; -- ;
+----------+----------+---------+----------------------+------------------+
+------------------------------------+
; Non-Global High Fan-Out Signals ;
+--------------------------+---------+
; Name ; Fan-Out ;
+--------------------------+---------+
; Time_EN ; 9 ;
; disp_drive[0]~70 ; 7 ;
; disp_drive[2]~66 ; 7 ;
; disp_drive[1]~56 ; 7 ;
; clk~24 ; 7 ;
; TimeSet_EN ; 5 ;
; always1~5sexp ; 4 ;
; auto_disp_drive[0] ; 4 ;
; auto_disp_drive[2] ; 4 ;
; auto_disp_drive[1] ; 4 ;
; timeset_disp_drive[0] ; 1 ;
; timeset_disp_drive[1] ; 1 ;
; timeset_disp_drive[2] ; 1 ;
; clk_200hz ; 1 ;
; time_disp_select[0]~reg0 ; 1 ;
; time_disp_select[1]~reg0 ; 1 ;
; time_disp_select[2]~reg0 ; 1 ;
; time_disp_select[3]~reg0 ; 1 ;
; time_disp_select[4]~reg0 ; 1 ;
; time_disp_select[5]~reg0 ; 1 ;
; disp_drive~39 ; 1 ;
; disp_drive~41 ; 1 ;
; disp_drive~43 ; 1 ;
; clk~13 ; 1 ;
+--------------------------+---------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 19 / 72 ( 26 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 8.50) ; Number of LABs (Total = 2) ;
+----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.50) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 1 ;
+-------------------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC7 ; disp_drive[0]~70, disp_drive[2]~66, disp_drive[1]~56, clk~24 ; time_disp_select[0] ;
; A ; LC6 ; disp_drive[0]~70, disp_drive[2]~66, disp_drive[1]~56, clk~24 ; time_disp_select[1] ;
; A ; LC5 ; disp_drive[0]~70, disp_drive[2]~66, disp_drive[1]~56, clk~24 ; time_disp_select[2] ;
; A ; LC3 ; disp_drive[0]~70, disp_drive[2]~66, disp_drive[1]~56, clk~24 ; time_disp_select[3] ;
; A ; LC2 ; disp_drive[0]~70, disp_drive[2]~66, disp_drive[1]~56, clk~24 ; time_disp_select[4] ;
; A ; LC1 ; disp_drive[0]~70, disp_drive[2]~66, disp_drive[1]~56, clk~24 ; time_disp_select[5] ;
; A ; LC4 ; disp_drive~39, disp_drive[0]~70, always1~5sexp, Time_EN, TimeSet_EN ; disp_drive[0]~70, time_disp_select[5]~reg0, time_disp_select[4]~reg0, time_disp_select[3]~reg0, time_disp_select[2]~reg0, time_disp_select[1]~reg0, time_disp_select[0]~reg0 ;
; A ; LC8 ; disp_drive~41, disp_drive[2]~66, always1~5sexp, Time_EN, TimeSet_EN ; disp_drive[2]~66, time_disp_select[5]~reg0, time_disp_select[4]~reg0, time_disp_select[3]~reg0, time_disp_select[2]~reg0, time_disp_select[1]~reg0, time_disp_select[0]~reg0 ;
; A ; LC9 ; auto_disp_drive[0], Time_EN, timeset_disp_drive[0] ; disp_drive[0]~70 ;
; A ; LC10 ; Time_EN, auto_disp_drive[2], timeset_disp_drive[2] ; disp_drive[2]~66 ;
; A ; LC11 ; clk_1khz, auto_disp_drive[2], auto_disp_drive[1], auto_disp_drive[0] ; auto_disp_drive[1], auto_disp_drive[2], auto_disp_drive[0], disp_drive~39 ;
; A ; LC12 ; disp_drive~43, disp_drive[1]~56, always1~5sexp, Time_EN, TimeSet_EN ; disp_drive[1]~56, time_disp_select[5]~reg0, time_disp_select[4]~reg0, time_disp_select[3]~reg0, time_disp_select[2]~reg0, time_disp_select[1]~reg0, time_disp_select[0]~reg0 ;
; A ; LC13 ; clk~13, clk~24, always1~5sexp, Time_EN, TimeSet_EN ; clk~24, time_disp_select[5]~reg0, time_disp_select[4]~reg0, time_disp_select[3]~reg0, time_disp_select[2]~reg0, time_disp_select[1]~reg0, time_disp_select[0]~reg0 ;
; A ; LC14 ; clk_1khz, auto_disp_drive[0], auto_disp_drive[2], auto_disp_drive[1] ; auto_disp_drive[1], auto_disp_drive[2], auto_disp_drive[0], disp_drive~41 ;
; A ; LC15 ; Time_EN, auto_disp_drive[1], timeset_disp_drive[1] ; disp_drive[1]~56 ;
; A ; LC16 ; clk_1khz, auto_disp_drive[2], auto_disp_drive[0], auto_disp_drive[1] ; auto_disp_drive[1], disp_drive~43, auto_disp_drive[2], auto_disp_drive[0] ;
; B ; LC25 ; Time_EN, clk_1khz, clk_200hz ; clk~24 ;
+-----+------------+----------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Sat Jul 15 21:02:11 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off time_disp_select -c time_disp_select
Info: Automatically selected device EPM7032SLC44-5 for design time_disp_select
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Jul 15 21:02:12 2006
Info: Elapsed time: 00:00:02
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