date_main.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "date_disp_clk register datecontrol:inst1\|day0\[3\] register datecontrol:inst1\|day0\[3\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"date_disp_clk\" has Internal fmax of 175.44 MHz between source register \"datecontrol:inst1\|day0\[3\]\" and destination register \"datecontrol:inst1\|day0\[3\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns datecontrol:inst1\|day0\[3\] 1 REG LC25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC25; Fanout = 3; REG Node = 'datecontrol:inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.700 ns datecontrol:inst1\|day0\[3\] 2 REG LC25 3 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC25; Fanout = 3; REG Node = 'datecontrol:inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.700 ns" { datecontrol:inst1|day0[3] datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 70.27 % " "Info: Total cell delay = 2.600 ns ( 70.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 29.73 % " "Info: Total interconnect delay = 1.100 ns ( 29.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.700 ns" { datecontrol:inst1|day0[3] datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { datecontrol:inst1|day0[3] datecontrol:inst1|day0[3] } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "date_disp_clk destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"date_disp_clk\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns date_disp_clk 1 CLK PIN_37 16 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 16; CLK Node = 'date_disp_clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { date_disp_clk } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 48 -80 88 64 "date_disp_clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns datecontrol:inst1\|day0\[3\] 2 REG LC25 3 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC25; Fanout = 3; REG Node = 'datecontrol:inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "0.500 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { date_disp_clk date_disp_clk~out datecontrol:inst1|day0[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "date_disp_clk source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"date_disp_clk\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns date_disp_clk 1 CLK PIN_37 16 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 16; CLK Node = 'date_disp_clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { date_disp_clk } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 48 -80 88 64 "date_disp_clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns datecontrol:inst1\|day0\[3\] 2 REG LC25 3 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC25; Fanout = 3; REG Node = 'datecontrol:inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "0.500 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { date_disp_clk date_disp_clk~out datecontrol:inst1|day0[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { date_disp_clk date_disp_clk~out datecontrol:inst1|day0[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { date_disp_clk date_disp_clk~out datecontrol:inst1|day0[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/datecontrol.v" 7 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.700 ns" { datecontrol:inst1|day0[3] datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { datecontrol:inst1|day0[3] datecontrol:inst1|day0[3] } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { date_disp_clk date_disp_clk~out datecontrol:inst1|day0[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { date_disp_clk datecontrol:inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { date_disp_clk date_disp_clk~out datecontrol:inst1|day0[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\] Date_Set_EN day_EN 5.000 ns register " "Info: tsu for register \"autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\]\" (data pin = \"Date_Set_EN\", clock pin = \"day_EN\") is 5.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest pin register " "Info: + Longest pin to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Date_Set_EN 1 PIN PIN_42 106 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_42; Fanout = 106; PIN Node = 'Date_Set_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { Date_Set_EN } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 104 -80 88 120 "Date_Set_EN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(2.600 ns) 4.200 ns autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\]~508 2 COMB LC43 1 " "Info: 2: + IC(1.400 ns) + CELL(2.600 ns) = 4.200 ns; Loc. = LC43; Fanout = 1; COMB Node = 'autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\]~508'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.000 ns" { Date_Set_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~508 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 5.100 ns autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\]~496 3 COMB LC44 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 5.100 ns; Loc. = LC44; Fanout = 1; COMB Node = 'autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\]~496'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "0.900 ns" { autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~508 autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~496 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 6.000 ns autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\] 4 REG LC45 62 " "Info: 4: + IC(0.000 ns) + CELL(0.900 ns) = 6.000 ns; Loc. = LC45; Fanout = 62; REG Node = 'autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "0.900 ns" { autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~496 autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 76.67 % " "Info: Total cell delay = 4.600 ns ( 76.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 23.33 % " "Info: Total interconnect delay = 1.400 ns ( 23.33 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "6.000 ns" { Date_Set_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~508 autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~496 autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { Date_Set_EN Date_Set_EN~out autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~508 autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~496 autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } { 0.000ns 0.000ns 1.400ns 0.000ns 0.000ns } { 0.000ns 0.200ns 2.600ns 0.900ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "day_EN destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"day_EN\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns day_EN 1 CLK PIN_40 12 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_40; Fanout = 12; CLK Node = 'day_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { day_EN } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 88 -80 88 104 "day_EN" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\] 2 REG LC45 62 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC45; Fanout = 62; REG Node = 'autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "0.500 ns" { day_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { day_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { day_EN day_EN~out autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "6.000 ns" { Date_Set_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~508 autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~496 autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { Date_Set_EN Date_Set_EN~out autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~508 autodate:inst|lpm_counter:month0_rtl_3|dffs[0]~496 autodate:inst|lpm_counter:month0_rtl_3|dffs[0] } { 0.000ns 0.000ns 1.400ns 0.000ns 0.000ns } { 0.000ns 0.200ns 2.600ns 0.900ns 0.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/