📄 date_main.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "day_EN register autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[2\] register autodate:inst\|day0\[0\] 111.11 MHz 9.0 ns Internal " "Info: Clock \"day_EN\" has Internal fmax of 111.11 MHz between source register \"autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[2\]\" and destination register \"autodate:inst\|day0\[0\]\" (period= 9.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest register register " "Info: + Longest register to register delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[2\] 1 REG LC14 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 49; REG Node = 'autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[2\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.100 ns) 4.400 ns rtl~1353 2 COMB SEXP58 3 " "Info: 2: + IC(1.300 ns) + CELL(3.100 ns) = 4.400 ns; Loc. = SEXP58; Fanout = 3; COMB Node = 'rtl~1353'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.400 ns" { autodate:inst|lpm_counter:month0_rtl_3|dffs[2] rtl~1353 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.600 ns) 7.000 ns autodate:inst\|day0\[0\] 3 REG LC56 43 " "Info: 3: + IC(0.000 ns) + CELL(2.600 ns) = 7.000 ns; Loc. = LC56; Fanout = 43; REG Node = 'autodate:inst\|day0\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "2.600 ns" { rtl~1353 autodate:inst|day0[0] } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/autodate.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 81.43 % " "Info: Total cell delay = 5.700 ns ( 81.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns 18.57 % " "Info: Total interconnect delay = 1.300 ns ( 18.57 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "7.000 ns" { autodate:inst|lpm_counter:month0_rtl_3|dffs[2] rtl~1353 autodate:inst|day0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.000 ns" { autodate:inst|lpm_counter:month0_rtl_3|dffs[2] rtl~1353 autodate:inst|day0[0] } { 0.000ns 1.300ns 0.000ns } { 0.000ns 3.100ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "day_EN destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"day_EN\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns day_EN 1 CLK PIN_40 12 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_40; Fanout = 12; CLK Node = 'day_EN'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { day_EN } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 88 -80 88 104 "day_EN" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns autodate:inst\|day0\[0\] 2 REG LC56 43 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC56; Fanout = 43; REG Node = 'autodate:inst\|day0\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "0.500 ns" { day_EN autodate:inst|day0[0] } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/autodate.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { day_EN autodate:inst|day0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { day_EN day_EN~out autodate:inst|day0[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "day_EN source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"day_EN\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns day_EN 1 CLK PIN_40 12 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_40; Fanout = 12; CLK Node = 'day_EN'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { day_EN } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 88 -80 88 104 "day_EN" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[2\] 2 REG LC14 49 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC14; Fanout = 49; REG Node = 'autodate:inst\|lpm_counter:month0_rtl_3\|dffs\[2\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "0.500 ns" { day_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { day_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { day_EN day_EN~out autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { day_EN autodate:inst|day0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { day_EN day_EN~out autodate:inst|day0[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { day_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { day_EN day_EN~out autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/autodate.v" 3 -1 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "7.000 ns" { autodate:inst|lpm_counter:month0_rtl_3|dffs[2] rtl~1353 autodate:inst|day0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.000 ns" { autodate:inst|lpm_counter:month0_rtl_3|dffs[2] rtl~1353 autodate:inst|day0[0] } { 0.000ns 1.300ns 0.000ns } { 0.000ns 3.100ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { day_EN autodate:inst|day0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { day_EN day_EN~out autodate:inst|day0[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "1.800 ns" { day_EN autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { day_EN day_EN~out autodate:inst|lpm_counter:month0_rtl_3|dffs[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register setdate:inst2\|disp_drive\[0\] register setdate:inst2\|disp_drive\[1\] 172.41 MHz 5.8 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 172.41 MHz between source register \"setdate:inst2\|disp_drive\[0\]\" and destination register \"setdate:inst2\|disp_drive\[1\]\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register register " "Info: + Longest register to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns setdate:inst2\|disp_drive\[0\] 1 REG LC15 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC15; Fanout = 31; REG Node = 'setdate:inst2\|disp_drive\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { setdate:inst2|disp_drive[0] } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/setdate.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.600 ns) 3.800 ns setdate:inst2\|disp_drive\[1\] 2 REG LC18 30 " "Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC18; Fanout = 30; REG Node = 'setdate:inst2\|disp_drive\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.800 ns" { setdate:inst2|disp_drive[0] setdate:inst2|disp_drive[1] } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/setdate.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 68.42 % " "Info: Total cell delay = 2.600 ns ( 68.42 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 31.58 % " "Info: Total interconnect delay = 1.200 ns ( 31.58 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.800 ns" { setdate:inst2|disp_drive[0] setdate:inst2|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { setdate:inst2|disp_drive[0] setdate:inst2|disp_drive[1] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 4.100 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 4.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_44 2 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_44; Fanout = 2; CLK Node = 'SW1'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { SW1 } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 248 -80 88 264 "SW1" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.700 ns) 4.100 ns setdate:inst2\|disp_drive\[1\] 2 REG LC18 30 " "Info: 2: + IC(1.200 ns) + CELL(2.700 ns) = 4.100 ns; Loc. = LC18; Fanout = 30; REG Node = 'setdate:inst2\|disp_drive\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.900 ns" { SW1 setdate:inst2|disp_drive[1] } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/setdate.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 70.73 % " "Info: Total cell delay = 2.900 ns ( 70.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 29.27 % " "Info: Total interconnect delay = 1.200 ns ( 29.27 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW1 setdate:inst2|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW1 SW1~out setdate:inst2|disp_drive[1] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 4.100 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 4.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_44 2 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_44; Fanout = 2; CLK Node = 'SW1'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { SW1 } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 248 -80 88 264 "SW1" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.700 ns) 4.100 ns setdate:inst2\|disp_drive\[0\] 2 REG LC15 31 " "Info: 2: + IC(1.200 ns) + CELL(2.700 ns) = 4.100 ns; Loc. = LC15; Fanout = 31; REG Node = 'setdate:inst2\|disp_drive\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.900 ns" { SW1 setdate:inst2|disp_drive[0] } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/setdate.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 70.73 % " "Info: Total cell delay = 2.900 ns ( 70.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 29.27 % " "Info: Total interconnect delay = 1.200 ns ( 29.27 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW1 setdate:inst2|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW1 SW1~out setdate:inst2|disp_drive[0] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW1 setdate:inst2|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW1 SW1~out setdate:inst2|disp_drive[1] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW1 setdate:inst2|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW1 SW1~out setdate:inst2|disp_drive[0] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" { } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/setdate.v" 3 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/setdate.v" 3 -1 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.800 ns" { setdate:inst2|disp_drive[0] setdate:inst2|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { setdate:inst2|disp_drive[0] setdate:inst2|disp_drive[1] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW1 setdate:inst2|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW1 SW1~out setdate:inst2|disp_drive[1] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW1 setdate:inst2|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW1 SW1~out setdate:inst2|disp_drive[0] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[0\] register setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[1\] 172.41 MHz 5.8 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 172.41 MHz between source register \"setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[0\]\" and destination register \"setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[1\]\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register register " "Info: + Longest register to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[0\] 1 REG LC22 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC22; Fanout = 4; REG Node = 'setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.600 ns) 3.800 ns setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[1\] 2 REG LC29 3 " "Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC29; Fanout = 3; REG Node = 'setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.800 ns" { setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 68.42 % " "Info: Total cell delay = 2.600 ns ( 68.42 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 31.58 % " "Info: Total interconnect delay = 1.200 ns ( 31.58 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.800 ns" { setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 4.100 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 4.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_3 12 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_3; Fanout = 12; CLK Node = 'SW2'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { SW2 } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 264 -80 88 280 "SW2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.700 ns) 4.100 ns setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[1\] 2 REG LC29 3 " "Info: 2: + IC(1.200 ns) + CELL(2.700 ns) = 4.100 ns; Loc. = LC29; Fanout = 3; REG Node = 'setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.900 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 70.73 % " "Info: Total cell delay = 2.900 ns ( 70.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 29.27 % " "Info: Total interconnect delay = 1.200 ns ( 29.27 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW2 SW2~out setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 4.100 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 4.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_3 12 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_3; Fanout = 12; CLK Node = 'SW2'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "" { SW2 } "NODE_NAME" } "" } } { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 264 -80 88 280 "SW2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.700 ns) 4.100 ns setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[0\] 2 REG LC22 4 " "Info: 2: + IC(1.200 ns) + CELL(2.700 ns) = 4.100 ns; Loc. = LC22; Fanout = 4; REG Node = 'setdate:inst2\|lpm_counter:day_set1_rtl_2\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.900 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 70.73 % " "Info: Total cell delay = 2.900 ns ( 70.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 29.27 % " "Info: Total interconnect delay = 1.200 ns ( 29.27 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW2 SW2~out setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW2 SW2~out setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW2 SW2~out setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "3.800 ns" { setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW2 SW2~out setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main_cmp.qrpt" Compiler "date_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/db/date_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/" "" "4.100 ns" { SW2 setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.100 ns" { SW2 SW2~out setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[0] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 0.200ns 2.700ns } } } } 0}
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