autodate.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_FULL_TCO_RESULT" "EN1 month1\[0\] month1\[0\]~reg0 2.800 ns register " "Info: tco from clock \"EN1\" to destination pin \"month1\[0\]\" through register \"month1\[0\]~reg0\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN1 source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"EN1\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN1 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { EN1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns month1\[0\]~reg0 2 REG LC1 57 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 57; REG Node = 'month1\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.100 ns" { EN1 month1[0]~reg0 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 107 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 month1[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out month1[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 107 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns month1\[0\]~reg0 1 REG LC1 57 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 57; REG Node = 'month1\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { month1[0]~reg0 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 107 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns month1\[0\] 2 PIN PIN_4 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'month1\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.200 ns" { month1[0]~reg0 month1[0] } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.200 ns" { month1[0]~reg0 month1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { month1[0]~reg0 month1[0] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 month1[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out month1[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.200 ns" { month1[0]~reg0 month1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { month1[0]~reg0 month1[0] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "EO1~reg0 EN2 EN1 -0.900 ns register " "Info: th for register \"EO1~reg0\" (data pin = \"EN2\", clock pin = \"EN1\") is -0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN1 destination 1.300 ns + Longest register " "Info: + Longest clock path from clock \"EN1\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN1 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { EN1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns EO1~reg0 2 REG LC30 1 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC30; Fanout = 1; REG Node = 'EO1~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.100 ns" { EN1 EO1~reg0 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 107 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 EO1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out EO1~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 107 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN2 1 PIN PIN_44 31 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 31; PIN Node = 'EN2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { EN2 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(2.600 ns) 3.900 ns EO1~reg0 2 REG LC30 1 " "Info: 2: + IC(0.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC30; Fanout = 1; REG Node = 'EO1~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "2.700 ns" { EN2 EO1~reg0 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 107 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 97.44 % " "Info: Total cell delay = 3.800 ns ( 97.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 2.56 % " "Info: Total interconnect delay = 0.100 ns ( 2.56 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "3.900 ns" { EN2 EO1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { EN2 EN2~out EO1~reg0 } { 0.000ns 0.000ns 0.100ns } { 0.000ns 1.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 EO1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out EO1~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "3.900 ns" { EN2 EO1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { EN2 EN2~out EO1~reg0 } { 0.000ns 0.000ns 0.100ns } { 0.000ns 1.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 20:09:23 2006 " "Info: Processing ended: Thu Jul 13 20:09:23 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}