autodate.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

+---------------+-------------+-----------+------+----------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                               ; To Clock ;
+---------------+-------------+-----------+------+----------------------------------+----------+
; N/A           ; None        ; -0.900 ns ; EN2  ; EO1~reg0                         ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:month0_rtl_0|dffs[1] ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:month0_rtl_0|dffs[2] ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:day0_rtl_2|dffs[3]   ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:day0_rtl_2|dffs[2]   ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:day0_rtl_2|dffs[1]   ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:day0_rtl_2|dffs[0]   ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; month1[0]~reg0                   ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:month0_rtl_0|dffs[3] ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:day1_rtl_1|dffs[1]   ; EN1      ;
; N/A           ; None        ; -0.900 ns ; EN2  ; lpm_counter:month0_rtl_0|dffs[0] ; EN1      ;
; N/A           ; None        ; -1.800 ns ; EN2  ; lpm_counter:day1_rtl_1|dffs[0]   ; EN1      ;
+---------------+-------------+-----------+------+----------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jul 13 20:09:22 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off autodate -c autodate
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "EN1" is an undefined clock
Info: Clock "EN1" has Internal fmax of 112.36 MHz between source register "lpm_counter:month0_rtl_0|dffs[1]" and destination register "lpm_counter:month0_rtl_0|dffs[0]" (period= 8.9 ns)
    Info: + Longest register to register delay is 6.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0|dffs[1]'
        Info: 2: + IC(1.100 ns) + CELL(3.100 ns) = 4.200 ns; Loc. = SEXP28; Fanout = 1; COMB Node = 'lpm_counter:month0_rtl_0|dffs[0]~287'
        Info: 3: + IC(0.000 ns) + CELL(2.600 ns) = 6.800 ns; Loc. = LC21; Fanout = 48; REG Node = 'lpm_counter:month0_rtl_0|dffs[0]'
        Info: Total cell delay = 5.700 ns ( 83.82 % )
        Info: Total interconnect delay = 1.100 ns ( 16.18 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "EN1" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC21; Fanout = 48; REG Node = 'lpm_counter:month0_rtl_0|dffs[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "EN1" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0|dffs[1]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "lpm_counter:month0_rtl_0|dffs[1]" (data pin = "EN2", clock pin = "EN1") is 4.300 ns
    Info: + Longest pin to register delay is 4.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 31; PIN Node = 'EN2'
        Info: 2: + IC(0.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC15; Fanout = 1; COMB Node = 'lpm_counter:month0_rtl_0|dffs[1]~299'
        Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0|dffs[1]'
        Info: Total cell delay = 4.700 ns ( 97.92 % )
        Info: Total interconnect delay = 0.100 ns ( 2.08 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "EN1" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0|dffs[1]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: tco from clock "EN1" to destination pin "month1[0]" through register "month1[0]~reg0" is 2.800 ns
    Info: + Longest clock path from clock "EN1" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 57; REG Node = 'month1[0]~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 57; REG Node = 'month1[0]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'month1[0]'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "EO1~reg0" (data pin = "EN2", clock pin = "EN1") is -0.900 ns
    Info: + Longest clock path from clock "EN1" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC30; Fanout = 1; REG Node = 'EO1~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 31; PIN Node = 'EN2'
        Info: 2: + IC(0.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC30; Fanout = 1; REG Node = 'EO1~reg0'
        Info: Total cell delay = 3.800 ns ( 97.44 % )
        Info: Total interconnect delay = 0.100 ns ( 2.56 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jul 13 20:09:23 2006
    Info: Elapsed time: 00:00:02