📄 setdate.fit.rpt
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; |lpm_counter:day_set0_rtl_3| ; 4 ; 0 ; |setdate|lpm_counter:day_set0_rtl_3 ;
; |lpm_counter:day_set1_rtl_2| ; 2 ; 0 ; |setdate|lpm_counter:day_set1_rtl_2 ;
; |lpm_counter:month_set0_rtl_1| ; 4 ; 0 ; |setdate|lpm_counter:month_set0_rtl_1 ;
; |lpm_counter:month_set1_rtl_0| ; 2 ; 0 ; |setdate|lpm_counter:month_set1_rtl_0 ;
+-----------------------------------+------------+------+---------------------------------------+
+-----------------------------------------------------------------------------------------------------------+
; Control Signals ;
+--------------------+----------+---------+--------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+--------------------+----------+---------+--------------+--------+----------------------+------------------+
; EN2 ; PIN_24 ; 2 ; Clock enable ; no ; -- ; -- ;
; SW1 ; PIN_43 ; 2 ; Clock ; yes ; On ; -- ;
; SW2 ; PIN_2 ; 12 ; Clock ; yes ; On ; -- ;
; disp_drive[0]~reg0 ; LC6 ; 14 ; Clock enable ; no ; -- ; -- ;
; disp_drive[1]~reg0 ; LC7 ; 13 ; Clock enable ; no ; -- ; -- ;
+--------------------+----------+---------+--------------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; SW1 ; PIN_43 ; 2 ; On ; -- ;
; SW2 ; PIN_2 ; 12 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+--------------------------------------+---------+
; Name ; Fan-Out ;
+--------------------------------------+---------+
; disp_drive[0]~reg0 ; 14 ;
; disp_drive[1]~reg0 ; 13 ;
; lpm_counter:day_set0_rtl_3|dffs[3] ; 5 ;
; lpm_counter:month_set0_rtl_1|dffs[3] ; 5 ;
; lpm_counter:day_set0_rtl_3|dffs[1] ; 5 ;
; lpm_counter:month_set0_rtl_1|dffs[1] ; 5 ;
; lpm_counter:day_set0_rtl_3|dffs[0] ; 5 ;
; lpm_counter:month_set0_rtl_1|dffs[0] ; 5 ;
; lpm_counter:day_set0_rtl_3|dffs[2] ; 4 ;
; lpm_counter:month_set0_rtl_1|dffs[2] ; 4 ;
; lpm_counter:month_set1_rtl_0|dffs[1] ; 3 ;
; lpm_counter:month_set1_rtl_0|dffs[0] ; 3 ;
; EN2 ; 2 ;
; lpm_counter:day_set1_rtl_2|dffs[0] ; 2 ;
; ~GND~3 ; 1 ;
; ~GND~2 ; 1 ;
; ~GND~1 ; 1 ;
; ~GND~0 ; 1 ;
; lpm_counter:day_set1_rtl_2|dffs[1] ; 1 ;
+--------------------------------------+---------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 14 / 72 ( 19 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 9.00) ; Number of LABs (Total = 2) ;
+----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 1 ;
+----------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC2 ; SW2, lpm_counter:day_set0_rtl_3|dffs[2], lpm_counter:day_set0_rtl_3|dffs[1], lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:day_set0_rtl_3|dffs[3], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:day_set0_rtl_3|dffs[1], lpm_counter:day_set0_rtl_3|dffs[2], lpm_counter:day_set0_rtl_3|dffs[3], day_set0[3] ;
; A ; LC5 ; SW2, lpm_counter:month_set0_rtl_1|dffs[2], lpm_counter:month_set0_rtl_1|dffs[1], lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:month_set0_rtl_1|dffs[3], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:month_set0_rtl_1|dffs[1], lpm_counter:month_set0_rtl_1|dffs[2], lpm_counter:month_set0_rtl_1|dffs[3], month_set0[3] ;
; A ; LC14 ; SW2, lpm_counter:day_set0_rtl_3|dffs[3], lpm_counter:day_set0_rtl_3|dffs[1], lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:day_set0_rtl_3|dffs[2], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:day_set0_rtl_3|dffs[2], day_set0[2], lpm_counter:day_set0_rtl_3|dffs[3] ;
; A ; LC10 ; SW2, lpm_counter:month_set0_rtl_1|dffs[3], lpm_counter:month_set0_rtl_1|dffs[1], lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:month_set0_rtl_1|dffs[2], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:month_set0_rtl_1|dffs[2], month_set0[2], lpm_counter:month_set0_rtl_1|dffs[3] ;
; A ; LC11 ; SW2, lpm_counter:day_set0_rtl_3|dffs[3], lpm_counter:day_set0_rtl_3|dffs[1], lpm_counter:day_set0_rtl_3|dffs[0], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:day_set0_rtl_3|dffs[1], day_set0[1], lpm_counter:day_set0_rtl_3|dffs[2], lpm_counter:day_set0_rtl_3|dffs[3] ;
; A ; LC12 ; SW2, lpm_counter:day_set1_rtl_2|dffs[0], disp_drive[1]~reg0, disp_drive[0]~reg0 ; day_set1[1] ;
; A ; LC16 ; SW2, lpm_counter:month_set0_rtl_1|dffs[3], lpm_counter:month_set0_rtl_1|dffs[1], lpm_counter:month_set0_rtl_1|dffs[0], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:month_set0_rtl_1|dffs[1], month_set0[1], lpm_counter:month_set0_rtl_1|dffs[2], lpm_counter:month_set0_rtl_1|dffs[3] ;
; A ; LC15 ; SW2, lpm_counter:month_set1_rtl_0|dffs[1], lpm_counter:month_set1_rtl_0|dffs[0], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:month_set1_rtl_0|dffs[0], lpm_counter:month_set1_rtl_0|dffs[1], month_set1[1] ;
; A ; LC13 ; SW2, lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:day_set0_rtl_3|dffs[3], lpm_counter:day_set0_rtl_3|dffs[2], lpm_counter:day_set0_rtl_3|dffs[1], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:day_set0_rtl_3|dffs[0], day_set0[0], lpm_counter:day_set0_rtl_3|dffs[1], lpm_counter:day_set0_rtl_3|dffs[2], lpm_counter:day_set0_rtl_3|dffs[3] ;
; A ; LC3 ; SW2, disp_drive[1]~reg0, disp_drive[0]~reg0 ; day_set1[0], lpm_counter:day_set1_rtl_2|dffs[1] ;
; A ; LC1 ; SW2, lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:month_set0_rtl_1|dffs[3], lpm_counter:month_set0_rtl_1|dffs[2], lpm_counter:month_set0_rtl_1|dffs[1], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:month_set0_rtl_1|dffs[0], month_set0[0], lpm_counter:month_set0_rtl_1|dffs[1], lpm_counter:month_set0_rtl_1|dffs[2], lpm_counter:month_set0_rtl_1|dffs[3] ;
; A ; LC8 ; SW2, lpm_counter:month_set1_rtl_0|dffs[1], lpm_counter:month_set1_rtl_0|dffs[0], disp_drive[1]~reg0, disp_drive[0]~reg0 ; lpm_counter:month_set1_rtl_0|dffs[0], month_set1[0], lpm_counter:month_set1_rtl_0|dffs[1] ;
; A ; LC7 ; SW1, disp_drive[0]~reg0, EN2 ; disp_drive[1], lpm_counter:month_set1_rtl_0|dffs[0], lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:day_set1_rtl_2|dffs[0], lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:month_set1_rtl_0|dffs[1], lpm_counter:month_set0_rtl_1|dffs[1], lpm_counter:day_set1_rtl_2|dffs[1], lpm_counter:day_set0_rtl_3|dffs[1], lpm_counter:month_set0_rtl_1|dffs[2], lpm_counter:day_set0_rtl_3|dffs[2], lpm_counter:month_set0_rtl_1|dffs[3], lpm_counter:day_set0_rtl_3|dffs[3] ;
; A ; LC6 ; SW1, EN2 ; disp_drive[0], disp_drive[1]~reg0, lpm_counter:month_set1_rtl_0|dffs[0], lpm_counter:month_set0_rtl_1|dffs[0], lpm_counter:day_set1_rtl_2|dffs[0], lpm_counter:day_set0_rtl_3|dffs[0], lpm_counter:month_set1_rtl_0|dffs[1], lpm_counter:month_set0_rtl_1|dffs[1], lpm_counter:day_set1_rtl_2|dffs[1], lpm_counter:day_set0_rtl_3|dffs[1], lpm_counter:month_set0_rtl_1|dffs[2], lpm_counter:day_set0_rtl_3|dffs[2], lpm_counter:month_set0_rtl_1|dffs[3], lpm_counter:day_set0_rtl_3|dffs[3] ;
; B ; LC21 ; ; month_set1[3] ;
; B ; LC19 ; ; month_set1[2] ;
; B ; LC18 ; ; day_set1[3] ;
; B ; LC17 ; ; day_set1[2] ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Thu Jul 13 14:01:44 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off setdate -c setdate
Info: Automatically selected device EPM7032SLC44-5 for design setdate
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Jul 13 14:01:45 2006
Info: Elapsed time: 00:00:01
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