main.fit.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.154 ns register register " "Info: Estimated most critical path is register to register delay of 2.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_main:inst4\|autodate:b2v_inst\|EO1 1 REG LAB_X35_Y14 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y14; Fanout = 21; REG Node = 'date_main:inst4\|autodate:b2v_inst\|EO1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.183 ns) 0.526 ns date_main:inst4\|datecontrol:b2v_inst1\|disp_select\[3\]~43 2 COMB LAB_X35_Y14 20 " "Info: 2: + IC(0.343 ns) + CELL(0.183 ns) = 0.526 ns; Loc. = LAB_X35_Y14; Fanout = 20; COMB Node = 'date_main:inst4\|datecontrol:b2v_inst1\|disp_select\[3\]~43'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.526 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.705 ns) 2.154 ns date_main:inst4\|datecontrol:b2v_inst1\|month1\[1\] 3 REG LAB_X34_Y12 1 " "Info: 3: + IC(0.923 ns) + CELL(0.705 ns) = 2.154 ns; Loc. = LAB_X34_Y12; Fanout = 1; REG Node = 'date_main:inst4\|datecontrol:b2v_inst1\|month1\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.628 ns" { date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|month1[1] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.888 ns 41.23 % " "Info: Total cell delay = 0.888 ns ( 41.23 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.266 ns 58.77 % " "Info: Total interconnect delay = 1.266 ns ( 58.77 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.154 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|month1[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "6 " "Info: Fitter placement operations ending: elapsed time = 6 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "2 " "Info: Fitter routing operations ending: elapsed time = 2 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 23:19:06 2006 " "Info: Processing ended: Sat Jul 15 23:19:06 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Info: Elapsed time: 00:00:37" {  } {  } 0}  } {  } 0}