main.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\] register alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\] 286.37 MHz 3.492 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 286.37 MHz between source register \"alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\]\" and destination register \"alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\]\" (period= 3.492 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.319 ns + Longest register register " "Info: + Longest register to register delay is 3.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\] 1 REG LC_X39_Y11_N7 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X39_Y11_N7; Fanout = 6; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(0.280 ns) 1.241 ns alarmclock:inst11\|LessThan~214 2 COMB LC_X36_Y11_N4 5 " "Info: 2: + IC(0.961 ns) + CELL(0.280 ns) = 1.241 ns; Loc. = LC_X36_Y11_N4; Fanout = 5; COMB Node = 'alarmclock:inst11\|LessThan~214'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.241 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.183 ns) 2.202 ns alarmclock:inst11\|hour_set0\[2\]~118 3 COMB LC_X36_Y11_N0 4 " "Info: 3: + IC(0.778 ns) + CELL(0.183 ns) = 2.202 ns; Loc. = LC_X36_Y11_N0; Fanout = 4; COMB Node = 'alarmclock:inst11\|hour_set0\[2\]~118'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.961 ns" { alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/alarmclock.v" 105 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.356 ns) + CELL(0.761 ns) 3.319 ns alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\] 4 REG LC_X36_Y11_N8 5 " "Info: 4: + IC(0.356 ns) + CELL(0.761 ns) = 3.319 ns; Loc. = LC_X36_Y11_N8; Fanout = 5; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.117 ns" { alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns 36.88 % " "Info: Total cell delay = 1.224 ns ( 36.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.095 ns 63.12 % " "Info: Total interconnect delay = 2.095 ns ( 63.12 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.961ns 0.778ns 0.356ns } { 0.000ns 0.280ns 0.183ns 0.761ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.007 ns - Smallest " "Info: - Smallest clock skew is -0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 2.855 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 2.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW2 1 CLK PIN_L2 64 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 64; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(0.542 ns) 2.855 ns alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\] 2 REG LC_X36_Y11_N8 5 " "Info: 2: + IC(1.588 ns) + CELL(0.542 ns) = 2.855 ns; Loc. = LC_X36_Y11_N8; Fanout = 5; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.130 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.38 % " "Info: Total cell delay = 1.267 ns ( 44.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns 55.62 % " "Info: Total interconnect delay = 1.588 ns ( 55.62 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.855 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.855 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 2.862 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW2 1 CLK PIN_L2 64 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 64; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.595 ns) + CELL(0.542 ns) 2.862 ns alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\] 2 REG LC_X39_Y11_N7 6 " "Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X39_Y11_N7; Fanout = 6; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.137 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.27 % " "Info: Total cell delay = 1.267 ns ( 44.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.595 ns 55.73 % " "Info: Total interconnect delay = 1.595 ns ( 55.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.862 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.862 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.855 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.855 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.862 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.862 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.961ns 0.778ns 0.356ns } { 0.000ns 0.280ns 0.183ns 0.761ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.855 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.855 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.862 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.862 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register date_main:inst4\|autodate:b2v_inst\|EO1 register date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\] 45.62 MHz 21.921 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 45.62 MHz between source register \"date_main:inst4\|autodate:b2v_inst\|EO1\" and destination register \"date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\]\" (period= 21.921 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.414 ns + Longest register register " "Info: + Longest register to register delay is 2.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_main:inst4\|autodate:b2v_inst\|EO1 1 REG LC_X35_Y14_N2 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y14_N2; Fanout = 21; REG Node = 'date_main:inst4\|autodate:b2v_inst\|EO1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.075 ns) 0.548 ns date_main:inst4\|datecontrol:b2v_inst1\|disp_select\[3\]~43 2 COMB LC_X35_Y14_N3 20 " "Info: 2: + IC(0.473 ns) + CELL(0.075 ns) = 0.548 ns; Loc. = LC_X35_Y14_N3; Fanout = 20; COMB Node = 'date_main:inst4\|datecontrol:b2v_inst1\|disp_select\[3\]~43'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.548 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(0.705 ns) 2.414 ns date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\] 3 REG LC_X35_Y12_N2 1 " "Info: 3: + IC(1.161 ns) + CELL(0.705 ns) = 2.414 ns; Loc. = LC_X35_Y12_N2; Fanout = 1; REG Node = 'date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.866 ns" { date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.780 ns 32.31 % " "Info: Total cell delay = 0.780 ns ( 32.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.634 ns 67.69 % " "Info: Total interconnect delay = 1.634 ns ( 67.69 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.473ns 1.161ns } { 0.000ns 0.075ns 0.705ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-19.341 ns - Smallest " "Info: - Smallest clock skew is -19.341 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 6.804 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 6.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Clock 1 CLK PIN_L3 37 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 37; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.698 ns) 3.207 ns fdiv:inst5\|f200hz 2 REG LC_X28_Y1_N8 93 " "Info: 2: + IC(1.681 ns) + CELL(0.698 ns) = 3.207 ns; Loc. = LC_X28_Y1_N8; Fanout = 93; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.379 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.055 ns) + CELL(0.542 ns) 6.804 ns date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\] 3 REG LC_X35_Y12_N2 1 " "Info: 3: + IC(3.055 ns) + CELL(0.542 ns) = 6.804 ns; Loc. = LC_X35_Y12_N2; Fanout = 1; REG Node = 'date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.597 ns" { fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns 30.39 % " "Info: Total cell delay = 2.068 ns ( 30.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.736 ns 69.61 % " "Info: Total interconnect delay = 4.736 ns ( 69.61 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.804 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.804 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.000ns 1.681ns 3.055ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 26.145 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 26.145 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Clock 1 CLK PIN_L3 37 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 37; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.698 ns) 3.207 ns fdiv:inst5\|f200hz 2 REG LC_X28_Y1_N8 93 " "Info: 2: + IC(1.681 ns) + CELL(0.698 ns) = 3.207 ns; Loc. = LC_X28_Y1_N8; Fanout = 93; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.379 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.076 ns) + CELL(0.698 ns) 6.981 ns fdiv:inst5\|f60hz 3 REG LC_X31_Y1_N7 1 " "Info: 3: + IC(3.076 ns) + CELL(0.698 ns) = 6.981 ns; Loc. = LC_X31_Y1_N7; Fanout = 1; REG Node = 'fdiv:inst5\|f60hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.774 ns" { fdiv:inst5|f200hz fdiv:inst5|f60hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.280 ns) 8.308 ns stopwatch:inst2\|F_out~8 4 COMB LC_X32_Y5_N9 9 " "Info: 4: + IC(1.047 ns) + CELL(0.280 ns) = 8.308 ns; Loc. = LC_X32_Y5_N9; Fanout = 9; COMB Node = 'stopwatch:inst2\|F_out~8'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.327 ns" { fdiv:inst5|f60hz stopwatch:inst2|F_out~8 } "NODE_NAME" } "" } } { "stopwatch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.284 ns) + CELL(0.698 ns) 12.290 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 5 REG LC_X33_Y9_N8 9 " "Info: 5: + IC(3.284 ns) + CELL(0.698 ns) = 12.290 ns; Loc. = LC_X33_Y9_N8; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.982 ns" { stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.273 ns) + CELL(0.698 ns) 17.261 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 6 REG LC_X36_Y9_N0 9 " "Info: 6: + IC(4.273 ns) + CELL(0.698 ns) = 17.261 ns; Loc. = LC_X36_Y9_N0; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.971 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.852 ns) + CELL(0.698 ns) 21.811 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 7 REG LC_X33_Y13_N4 14 " "Info: 7: + IC(3.852 ns) + CELL(0.698 ns) = 21.811 ns; Loc. = LC_X33_Y13_N4; Fanout = 14; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.550 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.792 ns) + CELL(0.542 ns) 26.145 ns date_main:inst4\|autodate:b2v_inst\|EO1 8 REG LC_X35_Y14_N2 21 " "Info: 8: + IC(3.792 ns) + CELL(0.542 ns) = 26.145 ns; Loc. = LC_X35_Y14_N2; Fanout = 21; REG Node = 'date_main:inst4\|autodate:b2v_inst\|EO1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.334 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.140 ns 19.66 % " "Info: Total cell delay = 5.140 ns ( 19.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "21.005 ns 80.34 % " "Info: Total interconnect delay = 21.005 ns ( 80.34 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "26.145 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.145 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.804 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.804 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.000ns 1.681ns 3.055ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "26.145 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.145 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 7 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.473ns 1.161ns } { 0.000ns 0.075ns 0.705ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.804 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.804 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.000ns 1.681ns 3.055ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "26.145 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.145 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW3 register date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\] register date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\] 155.79 MHz 6.419 ns Internal " "Info: Clock \"SW3\" has Internal fmax of 155.79 MHz between source register \"date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\]\" and destination register \"date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\]\" (period= 6.419 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.253 ns + Longest register register " "Info: + Longest register to register delay is 6.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\] 1 REG LC_X36_Y13_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y13_N3; Fanout = 5; REG Node = 'date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.280 ns) 1.325 ns date_main:inst4\|autodate:b2v_inst\|always0~575 2 COMB LC_X36_Y12_N6 2 " "Info: 2: + IC(1.045 ns) + CELL(0.280 ns) = 1.325 ns; Loc. = LC_X36_Y12_N6; Fanout = 2; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|always0~575'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.325 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.366 ns) 2.516 ns date_main:inst4\|autodate:b2v_inst\|always0~577 3 COMB LC_X35_Y12_N4 3 " "Info: 3: + IC(0.825 ns) + CELL(0.366 ns) = 2.516 ns; Loc. = LC_X35_Y12_N4; Fanout = 3; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|always0~577'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.191 ns" { date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.205 ns) + CELL(0.183 ns) 3.904 ns date_main:inst4\|autodate:b2v_inst\|month1\[0\]~199 4 COMB LC_X34_Y13_N1 2 " "Info: 4: + IC(1.205 ns) + CELL(0.183 ns) = 3.904 ns; Loc. = LC_X34_Y13_N1; Fanout = 2; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|month1\[0\]~199'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.388 ns" { date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.366 ns) 4.803 ns date_main:inst4\|autodate:b2v_inst\|month0\[0\]~524 5 COMB LC_X35_Y13_N9 1 " "Info: 5: + IC(0.533 ns) + CELL(0.366 ns) = 4.803 ns; Loc. = LC_X35_Y13_N9; Fanout = 1; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|month0\[0\]~524'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.899 ns" { date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.075 ns) 5.200 ns date_main:inst4\|autodate:b2v_inst\|month0\[0\]~525 6 COMB LC_X35_Y13_N4 4 " "Info: 6: + IC(0.322 ns) + CELL(0.075 ns) = 5.200 ns; Loc. = LC_X35_Y13_N4; Fanout = 4; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|month0\[0\]~525'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.397 ns" { date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main:inst4|autodate:b2v_inst|month0[0]~525 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.705 ns) 6.253 ns date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\] 7 REG LC_X35_Y13_N3 6 " "Info: 7: + IC(0.348 ns) + CELL(0.705 ns) = 6.253 ns; Loc. = LC_X35_Y13_N3; Fanout = 6; REG Node = 'date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.053 ns" { date_main:inst4|autodate:b2v_inst|month0[0]~525 date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.975 ns 31.58 % " "Info: Total cell delay = 1.975 ns ( 31.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.278 ns 68.42 % " "Info: Total interconnect delay = 4.278 ns ( 68.42 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.253 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main:inst4|autodate:b2v_inst|month0[0]~525 date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.253 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main: