main.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|clk " "Info: Node \"time_disp_select:inst6\|clk\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|disp_drive\[2\] " "Info: Node \"time_disp_select:inst6\|disp_drive\[2\]\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|disp_drive\[0\] " "Info: Node \"time_disp_select:inst6\|disp_drive\[0\]\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|disp_drive\[1\] " "Info: Node \"time_disp_select:inst6\|disp_drive\[1\]\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|Data\[1\] " "Info: Node \"disp_data_mux:inst8\|Data\[1\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}