main.map.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

; hour_counter.v                   ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v      ;
; minute_counter.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v    ;
; second_counter.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v    ;
; time_mux.v                       ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_mux.v          ;
; timeset.v                        ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v           ;
; stopwatch.v                      ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v         ;
; disp_data_mux.v                  ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v     ;
; date_main.v                      ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/date_main.v         ;
; autodate.v                       ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v          ;
; datecontrol.v                    ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v       ;
; setdate.v                        ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/setdate.v           ;
; time_disp_select.v               ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v  ;
; lpm_counter.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; db/cntr_e08.tdf                  ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf     ;
; db/cntr_jd7.tdf                  ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_jd7.tdf     ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------+-------------------+
; Resource                          ; Usage             ;
+-----------------------------------+-------------------+
; Logic cells                       ; 501               ;
; Total combinational functions     ; 485               ;
; Total 4-input functions           ; 173               ;
; Total 3-input functions           ; 89                ;
; Total 2-input functions           ; 27                ;
; Total 1-input functions           ; 196               ;
; Total 0-input functions           ; 0                 ;
; Combinational cells for routing   ; 0                 ;
; Total registers                   ; 256               ;
; Total logic cells in carry chains ; 196               ;
; I/O pins                          ; 18                ;
; Maximum fan-out node              ; fdiv:inst5|f200hz ;
; Maximum fan-out                   ; 93                ;
; Total fan-out                     ; 1991              ;
; Average fan-out                   ; 3.84              ;
+-----------------------------------+-------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 23:18:01 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off main -c main
Warning: Can't analyze file -- file E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.v is missing
Info: Found 1 design units, including 1 entities, in source file main.bdf
    Info: Found entity 1: main
Info: Using design file alarmclock.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: alarmclock
Info: Using design file maincontrol.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: maincontrol
Info: Using design file fdiv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fdiv
Info: Using design file time_auto_and_set.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: time_auto_and_set
Info: Using design file timepiece_main.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: timepiece_main
Info: Using design file hour_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: hour_counter
Info: Using design file minute_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: minute_counter
Info: Using design file second_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: second_counter
Info: Using design file time_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: time_mux
Info: Using design file timeset.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: timeset
Warning: Verilog HDL unsupported feature warning at timeset.v(36): Initial Construct is not supported and will be ignored
Info: Using design file stopwatch.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: stopwatch
Info: Using design file disp_data_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: disp_data_mux
Warning: Verilog HDL Always Construct warning at disp_data_mux.v(97): variable "Data" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at disp_data_mux.v(40): variable disp_select may not be assigned a new value in every possible path through the Always Construct.  Variable disp_select holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at disp_data_mux.v(40): variable Data may not be assigned a new value in every possible path through the Always Construct.  Variable Data holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file date_main.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: date_main
Info: Using design file autodate.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: autodate
Info: Using design file datecontrol.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: datecontrol
Info: Using design file setdate.v, which is not specified as a design file for the current