timeset.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_TSU_RESULT" "disp_drive\[0\]~reg0 TimeSet_EN SW1 2.900 ns register " "Info: tsu for register \"disp_drive\[0\]~reg0\" (data pin = \"TimeSet_EN\", clock pin = \"SW1\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns + Longest pin register " "Info: + Longest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns TimeSet_EN 1 PIN PIN_92 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_92; Fanout = 3; PIN Node = 'TimeSet_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { TimeSet_EN } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns disp_drive\[0\]~reg0 2 REG LC1 27 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.700 ns" { TimeSet_EN disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 71.79 % " "Info: Total cell delay = 2.800 ns ( 71.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 28.21 % " "Info: Total interconnect delay = 1.100 ns ( 28.21 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.900 ns" { TimeSet_EN disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { TimeSet_EN TimeSet_EN~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"SW1\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW1 1 CLK PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { SW1 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns disp_drive\[0\]~reg0 2 REG LC1 27 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.500 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.900 ns" { TimeSet_EN disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { TimeSet_EN TimeSet_EN~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SW2 minute_set0\[3\] lpm_counter:minute_set0_rtl_3\|dffs\[3\] 3.200 ns register " "Info: tco from clock \"SW2\" to destination pin \"minute_set0\[3\]\" through register \"lpm_counter:minute_set0_rtl_3\|dffs\[3\]\" is 3.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"SW2\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW2 1 CLK PIN_90 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { SW2 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns lpm_counter:minute_set0_rtl_3\|dffs\[3\] 2 REG LC19 8 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC19; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.500 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:minute_set0_rtl_3\|dffs\[3\] 1 REG LC19 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { lpm_counter:minute_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns minute_set0\[3\] 2 PIN PIN_35 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'minute_set0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.200 ns" { lpm_counter:minute_set0_rtl_3|dffs[3] minute_set0[3] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.200 ns" { lpm_counter:minute_set0_rtl_3|dffs[3] minute_set0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:minute_set0_rtl_3|dffs[3] minute_set0[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_3|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.200 ns" { lpm_counter:minute_set0_rtl_3|dffs[3] minute_set0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:minute_set0_rtl_3|dffs[3] minute_set0[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "disp_drive\[0\]~reg0 TimeSet_EN SW1 -0.400 ns register " "Info: th for register \"disp_drive\[0\]~reg0\" (data pin = \"TimeSet_EN\", clock pin = \"SW1\") is -0.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 1.800 ns + Longest register " "Info: + Longest clock path from clock \"SW1\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW1 1 CLK PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { SW1 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns disp_drive\[0\]~reg0 2 REG LC1 27 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "0.500 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns TimeSet_EN 1 PIN PIN_92 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_92; Fanout = 3; PIN Node = 'TimeSet_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "" { TimeSet_EN } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns disp_drive\[0\]~reg0 2 REG LC1 27 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.700 ns" { TimeSet_EN disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/timeset.v" 48 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 71.79 % " "Info: Total cell delay = 2.800 ns ( 71.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 28.21 % " "Info: Total interconnect delay = 1.100 ns ( 28.21 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.900 ns" { TimeSet_EN disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { TimeSet_EN TimeSet_EN~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "1.800 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset_cmp.qrpt" Compiler "timeset" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/db/timeset.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timeset/" "" "3.900 ns" { TimeSet_EN disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { TimeSet_EN TimeSet_EN~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 17:44:35 2006 " "Info: Processing ended: Sat Jul 15 17:44:35 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}