timeset.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

; N/A   ; None         ; 3.200 ns   ; lpm_counter:hour_set1_rtl_0|dffs[1]   ; hour_set1[1]   ; SW2        ;
; N/A   ; None         ; 3.200 ns   ; lpm_counter:minute_set0_rtl_3|dffs[0] ; minute_set0[0] ; SW2        ;
; N/A   ; None         ; 3.200 ns   ; lpm_counter:hour_set0_rtl_1|dffs[0]   ; hour_set0[0]   ; SW2        ;
; N/A   ; None         ; 3.200 ns   ; lpm_counter:second_set0_rtl_5|dffs[0] ; second_set0[0] ; SW2        ;
; N/A   ; None         ; 3.200 ns   ; lpm_counter:second_set1_rtl_4|dffs[0] ; second_set1[0] ; SW2        ;
; N/A   ; None         ; 3.200 ns   ; lpm_counter:minute_set1_rtl_2|dffs[0] ; minute_set1[0] ; SW2        ;
; N/A   ; None         ; 3.200 ns   ; lpm_counter:hour_set1_rtl_0|dffs[0]   ; hour_set1[0]   ; SW2        ;
; N/A   ; None         ; 3.200 ns   ; disp_drive[2]~reg0                    ; disp_drive[2]  ; SW1        ;
; N/A   ; None         ; 3.200 ns   ; disp_drive[1]~reg0                    ; disp_drive[1]  ; SW1        ;
; N/A   ; None         ; 3.200 ns   ; disp_drive[0]~reg0                    ; disp_drive[0]  ; SW1        ;
+-------+--------------+------------+---------------------------------------+----------------+------------+


+--------------------------------------------------------------------------------------+
; th                                                                                   ;
+---------------+-------------+-----------+------------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                 ; To Clock ;
+---------------+-------------+-----------+------------+--------------------+----------+
; N/A           ; None        ; -0.400 ns ; TimeSet_EN ; disp_drive[0]~reg0 ; SW1      ;
; N/A           ; None        ; -0.400 ns ; TimeSet_EN ; disp_drive[1]~reg0 ; SW1      ;
; N/A           ; None        ; -0.400 ns ; TimeSet_EN ; disp_drive[2]~reg0 ; SW1      ;
+---------------+-------------+-----------+------------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 17:44:34 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off timeset -c timeset
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "SW1" is an undefined clock
    Info: Assuming node "SW2" is an undefined clock
Info: Clock "SW1" has Internal fmax of 172.41 MHz between source register "disp_drive[0]~reg0" and destination register "disp_drive[2]~reg0" (period= 5.8 ns)
    Info: + Longest register to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive[0]~reg0'
        Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 27; REG Node = 'disp_drive[2]~reg0'
        Info: Total cell delay = 2.600 ns ( 68.42 % )
        Info: Total interconnect delay = 1.200 ns ( 31.58 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW1" to destination register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC3; Fanout = 27; REG Node = 'disp_drive[2]~reg0'
            Info: Total cell delay = 1.800 ns ( 100.00 % )
        Info: - Longest clock path from clock "SW1" to source register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive[0]~reg0'
            Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: Clock "SW2" has Internal fmax of 175.44 MHz between source register "lpm_counter:minute_set0_rtl_3|dffs[0]" and destination register "lpm_counter:minute_set0_rtl_3|dffs[1]" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3|dffs[0]'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC30; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_3|dffs[1]'
        Info: Total cell delay = 2.600 ns ( 70.27 % )
        Info: Total interconnect delay = 1.100 ns ( 29.73 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW2" to destination register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC30; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_3|dffs[1]'
            Info: Total cell delay = 1.800 ns ( 100.00 % )
        Info: - Longest clock path from clock "SW2" to source register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC21; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3|dffs[0]'
            Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "disp_drive[0]~reg0" (data pin = "TimeSet_EN", clock pin = "SW1") is 2.900 ns
    Info: + Longest pin to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_92; Fanout = 3; PIN Node = 'TimeSet_EN'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 2.800 ns ( 71.79 % )
        Info: Total interconnect delay = 1.100 ns ( 28.21 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "SW1" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
Info: tco from clock "SW2" to destination pin "minute_set0[3]" through register "lpm_counter:minute_set0_rtl_3|dffs[3]" is 3.200 ns
    Info: + Longest clock path from clock "SW2" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC19; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3|dffs[3]'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 8; REG Node = 'lpm_counter:minute_set0_rtl_3|dffs[3]'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'minute_set0[3]'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "disp_drive[0]~reg0" (data pin = "TimeSet_EN", clock pin = "SW1") is -0.400 ns
    Info: + Longest clock path from clock "SW1" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'SW1'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_92; Fanout = 3; PIN Node = 'TimeSet_EN'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 27; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 2.800 ns ( 71.79 % )
        Info: Total interconnect delay = 1.100 ns ( 28.21 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jul 15 17:44:35 2006
    Info: Elapsed time: 00:00:02