alarmclock.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_TH_RESULT" "disp_drive\[0\] EN SW1 1.800 ns register " "Info: th for register \"disp_drive\[0\]\" (data pin = \"EN\", clock pin = \"SW1\") is 1.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 4.000 ns + Longest register " "Info: + Longest clock path from clock \"SW1\" to destination register is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_47 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { SW1 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.700 ns) 4.000 ns disp_drive\[0\] 2 REG LC18 31 " "Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.800 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 72.50 % " "Info: Total cell delay = 2.900 ns ( 72.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 27.50 % " "Info: Total interconnect delay = 1.100 ns ( 27.50 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EN 1 PIN PIN_46 5 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_46; Fanout = 5; PIN Node = 'EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { EN } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns disp_drive\[0\] 2 REG LC18 31 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.700 ns" { EN disp_drive[0] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 71.79 % " "Info: Total cell delay = 2.800 ns ( 71.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 28.21 % " "Info: Total interconnect delay = 1.100 ns ( 28.21 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.900 ns" { EN disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { EN EN~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.900 ns" { EN disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { EN EN~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 20:29:49 2006 " "Info: Processing ended: Sat Jul 15 20:29:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}