alarmclock.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register lpm_counter:second_set1_rtl_1\|dffs\[1\] register lpm_counter:second_set1_rtl_1\|dffs\[0\] 172.41 MHz 5.8 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 172.41 MHz between source register \"lpm_counter:second_set1_rtl_1\|dffs\[1\]\" and destination register \"lpm_counter:second_set1_rtl_1\|dffs\[0\]\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register register " "Info: + Longest register to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:second_set1_rtl_1\|dffs\[1\] 1 REG LC11 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 7; REG Node = 'lpm_counter:second_set1_rtl_1\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { lpm_counter:second_set1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.600 ns) 3.800 ns lpm_counter:second_set1_rtl_1\|dffs\[0\] 2 REG LC13 8 " "Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC13; Fanout = 8; REG Node = 'lpm_counter:second_set1_rtl_1\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.800 ns" { lpm_counter:second_set1_rtl_1|dffs[1] lpm_counter:second_set1_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 68.42 % " "Info: Total cell delay = 2.600 ns ( 68.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 31.58 % " "Info: Total interconnect delay = 1.200 ns ( 31.58 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.800 ns" { lpm_counter:second_set1_rtl_1|dffs[1] lpm_counter:second_set1_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { lpm_counter:second_set1_rtl_1|dffs[1] lpm_counter:second_set1_rtl_1|dffs[0] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW2 1 CLK PIN_90 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { SW2 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns lpm_counter:second_set1_rtl_1\|dffs\[0\] 2 REG LC13 8 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC13; Fanout = 8; REG Node = 'lpm_counter:second_set1_rtl_1\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "0.500 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:second_set1_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW2 1 CLK PIN_90 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { SW2 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns lpm_counter:second_set1_rtl_1\|dffs\[1\] 2 REG LC11 7 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC11; Fanout = 7; REG Node = 'lpm_counter:second_set1_rtl_1\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "0.500 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:second_set1_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:second_set1_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:second_set1_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.800 ns" { lpm_counter:second_set1_rtl_1|dffs[1] lpm_counter:second_set1_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { lpm_counter:second_set1_rtl_1|dffs[1] lpm_counter:second_set1_rtl_1|dffs[0] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:second_set1_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:second_set1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:second_set1_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "disp_drive\[0\] EN SW1 0.700 ns register " "Info: tsu for register \"disp_drive\[0\]\" (data pin = \"EN\", clock pin = \"SW1\") is 0.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns + Longest pin register " "Info: + Longest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EN 1 PIN PIN_46 5 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_46; Fanout = 5; PIN Node = 'EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { EN } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns disp_drive\[0\] 2 REG LC18 31 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.700 ns" { EN disp_drive[0] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 71.79 % " "Info: Total cell delay = 2.800 ns ( 71.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 28.21 % " "Info: Total interconnect delay = 1.100 ns ( 28.21 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.900 ns" { EN disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { EN EN~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 4.000 ns - Shortest register " "Info: - Shortest clock path from clock \"SW1\" to destination register is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_47 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_47; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { SW1 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.700 ns) 4.000 ns disp_drive\[0\] 2 REG LC18 31 " "Info: 2: + IC(1.100 ns) + CELL(2.700 ns) = 4.000 ns; Loc. = LC18; Fanout = 31; REG Node = 'disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.800 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns 72.50 % " "Info: Total cell delay = 2.900 ns ( 72.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 27.50 % " "Info: Total interconnect delay = 1.100 ns ( 27.50 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "3.900 ns" { EN disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { EN EN~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.000 ns" { SW1 disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { SW1 SW1~out disp_drive[0] } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SW2 alarm lpm_counter:minute_set0_rtl_2\|dffs\[1\] 12.400 ns register " "Info: tco from clock \"SW2\" to destination pin \"alarm\" through register \"lpm_counter:minute_set0_rtl_2\|dffs\[1\]\" is 12.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"SW2\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SW2 1 CLK PIN_90 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_90; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { SW2 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns lpm_counter:minute_set0_rtl_2\|dffs\[1\] 2 REG LC37 7 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC37; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_2\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "0.500 ns" { SW2 lpm_counter:minute_set0_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_2|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.400 ns + Longest register pin " "Info: + Longest register to pin delay is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:minute_set0_rtl_2\|dffs\[1\] 1 REG LC37 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 7; REG Node = 'lpm_counter:minute_set0_rtl_2\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { lpm_counter:minute_set0_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 4.600 ns always0~68 2 COMB LC38 1 " "Info: 2: + IC(1.100 ns) + CELL(3.500 ns) = 4.600 ns; Loc. = LC38; Fanout = 1; COMB Node = 'always0~68'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.600 ns" { lpm_counter:minute_set0_rtl_2|dffs[1] always0~68 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 9.200 ns always0~117 3 COMB LC49 1 " "Info: 3: + IC(1.100 ns) + CELL(3.500 ns) = 9.200 ns; Loc. = LC49; Fanout = 1; COMB Node = 'always0~117'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.600 ns" { always0~68 always0~117 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.400 ns alarm 4 PIN PIN_63 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.400 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'alarm'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "0.200 ns" { always0~117 alarm } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 76.60 % " "Info: Total cell delay = 7.200 ns ( 76.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 23.40 % " "Info: Total interconnect delay = 2.200 ns ( 23.40 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "9.400 ns" { lpm_counter:minute_set0_rtl_2|dffs[1] always0~68 always0~117 alarm } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.400 ns" { lpm_counter:minute_set0_rtl_2|dffs[1] always0~68 always0~117 alarm } { 0.000ns 1.100ns 1.100ns 0.000ns } { 0.000ns 3.500ns 3.500ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "1.800 ns" { SW2 lpm_counter:minute_set0_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { SW2 SW2~out lpm_counter:minute_set0_rtl_2|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "9.400 ns" { lpm_counter:minute_set0_rtl_2|dffs[1] always0~68 always0~117 alarm } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.400 ns" { lpm_counter:minute_set0_rtl_2|dffs[1] always0~68 always0~117 alarm } { 0.000ns 1.100ns 1.100ns 0.000ns } { 0.000ns 3.500ns 3.500ns 0.200ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "minute0\[1\] alarm 9.600 ns Longest " "Info: Longest tpd from source pin \"minute0\[1\]\" to destination pin \"alarm\" is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns minute0\[1\] 1 PIN PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 1; PIN Node = 'minute0\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "" { minute0[1] } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 4.800 ns always0~68 2 COMB LC38 1 " "Info: 2: + IC(1.100 ns) + CELL(3.500 ns) = 4.800 ns; Loc. = LC38; Fanout = 1; COMB Node = 'always0~68'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.600 ns" { minute0[1] always0~68 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 9.400 ns always0~117 3 COMB LC49 1 " "Info: 3: + IC(1.100 ns) + CELL(3.500 ns) = 9.400 ns; Loc. = LC49; Fanout = 1; COMB Node = 'always0~117'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "4.600 ns" { always0~68 always0~117 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.600 ns alarm 4 PIN PIN_63 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.600 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'alarm'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "0.200 ns" { always0~117 alarm } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/alarmclock.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 77.08 % " "Info: Total cell delay = 7.400 ns ( 77.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 22.92 % " "Info: Total interconnect delay = 2.200 ns ( 22.92 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock_cmp.qrpt" Compiler "alarmclock" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/db/alarmclock.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/alarmclock/" "" "9.600 ns" { minute0[1] always0~68 always0~117 alarm } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { minute0[1] minute0[1]~out always0~68 always0~117 alarm } { 0.000ns 0.000ns 1.100ns 1.100ns 0.000ns } { 0.000ns 0.200ns 3.500ns 3.500ns 0.200ns } } }  } 0}