timepiece_main.map.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

+--------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                  ;
+----------------------------------------+------------+------+-------------------------------------------------------------------------+
; Compilation Hierarchy Node             ; Macrocells ; Pins ; Full Hierarchy Name                                                     ;
+----------------------------------------+------------+------+-------------------------------------------------------------------------+
; |timepiece_main                        ; 38         ; 27   ; |timepiece_main                                                         ;
;    |hour_counter:b2v_inst|             ; 12         ; 0    ; |timepiece_main|hour_counter:b2v_inst                                   ;
;       |lpm_counter:hour_data0_rtl_0|   ; 6          ; 0    ; |timepiece_main|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0      ;
;       |lpm_counter:hour_data1_rtl_1|   ; 4          ; 0    ; |timepiece_main|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1      ;
;    |minute_counter:b2v_inst1|          ; 11         ; 0    ; |timepiece_main|minute_counter:b2v_inst1                                ;
;       |lpm_counter:minute_data0_rtl_2| ; 4          ; 0    ; |timepiece_main|minute_counter:b2v_inst1|lpm_counter:minute_data0_rtl_2 ;
;       |lpm_counter:minute_data1_rtl_3| ; 5          ; 0    ; |timepiece_main|minute_counter:b2v_inst1|lpm_counter:minute_data1_rtl_3 ;
;    |second_counter:b2v_inst2|          ; 11         ; 0    ; |timepiece_main|second_counter:b2v_inst2                                ;
;       |lpm_counter:second_data0_rtl_4| ; 4          ; 0    ; |timepiece_main|second_counter:b2v_inst2|lpm_counter:second_data0_rtl_4 ;
;       |lpm_counter:second_data1_rtl_5| ; 5          ; 0    ; |timepiece_main|second_counter:b2v_inst2|lpm_counter:second_data1_rtl_5 ;
+----------------------------------------+------------+------+-------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.map.eqn.


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                    ;
+----------------------------------+-----------------+--------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                                         ;
+----------------------------------+-----------------+--------------------------------------------------------------------------------------+
; timepiece_main.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v ;
; hour_counter.v                   ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v   ;
; minute_counter.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/minute_counter.v ;
; second_counter.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v ;
; lpm_counter.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf                          ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc                         ;
; lpm_decode.inc                   ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc                           ;
; lpm_add_sub.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc                          ;
; cmpconst.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc                             ;
; lpm_compare.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc                          ;
; lpm_counter.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc                          ;
; dffeea.inc                       ; yes             ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc                               ;
; alt_synch_counter.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc                    ;
; alt_synch_counter_f.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc                  ;
; alt_counter_f10ke.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc                    ;
; alt_counter_stratix.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc                  ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc                            ;
+----------------------------------+-----------------+--------------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 38                   ;
; Total registers      ; 23                   ;
; I/O pins             ; 27                   ;
; Parallel expanders   ; 11                   ;
; Maximum fan-out node ; Timepiece_EN         ;
; Maximum fan-out      ; 30                   ;
; Total fan-out        ; 272                  ;
; Average fan-out      ; 4.18                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 17:07:17 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off timepiece_main -c timepiece_main
Info: Found 1 design units, including 1 entities, in source file timepiece_main.v
    Info: Found entity 1: timepiece_main
Info: Using design file hour_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: hour_counter
Info: Using design file minute_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: minute_counter
Info: Using design file second_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: second_counter
Info: Inferred 6 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour_counter:b2v_inst|hour_data0[0]~16"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour_counter:b2v_inst|hour_data1[0]~24"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "minute_counter:b2v_inst1|minute_data0[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "minute_counter:b2v_inst1|minute_data1[0]~16"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "second_counter:b2v_inst2|second_data0[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "second_counter:b2v_inst2|second_data1[0]~16"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Warning: Reduced register "hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "minute_counter:b2v_inst1|lpm_counter:minute_data1_rtl_3|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "second_counter:b2v_inst2|lpm_counter:second_data1_rtl_5|dffs[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "hour1[3]" stuck at GND
    Warning: Pin "hour1[2]" stuck at GND
    Warning: Pin "minute1[3]" stuck at GND
    Warning: Pin "second1[3]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Implemented 65 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 25 output pins
    Info: Implemented 38 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Sat Jul 15 17:07:22 2006
    Info: Elapsed time: 00:00:06