fdiv.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "f200hz~reg0 " "Info: Detected ripple clock \"f200hz~reg0\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 25 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "f200hz~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:CNT3_rtl_2\|dffs\[0\] register lpm_counter:CNT3_rtl_2\|dffs\[6\] 96.15 MHz 10.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 96.15 MHz between source register \"lpm_counter:CNT3_rtl_2\|dffs\[0\]\" and destination register \"lpm_counter:CNT3_rtl_2\|dffs\[6\]\" (period= 10.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT3_rtl_2\|dffs\[0\] 1 REG LC5 72 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 72; REG Node = 'lpm_counter:CNT3_rtl_2\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "" { lpm_counter:CNT3_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(3.000 ns) 4.700 ns lpm_counter:CNT3_rtl_2\|dffs\[6\]~1401 2 COMB LC52 1 " "Info: 2: + IC(1.700 ns) + CELL(3.000 ns) = 4.700 ns; Loc. = LC52; Fanout = 1; COMB Node = 'lpm_counter:CNT3_rtl_2\|dffs\[6\]~1401'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "4.700 ns" { lpm_counter:CNT3_rtl_2|dffs[0] lpm_counter:CNT3_rtl_2|dffs[6]~1401 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 5.800 ns lpm_counter:CNT3_rtl_2\|dffs\[6\]~1400 3 COMB LC53 1 " "Info: 3: + IC(0.000 ns) + CELL(1.100 ns) = 5.800 ns; Loc. = LC53; Fanout = 1; COMB Node = 'lpm_counter:CNT3_rtl_2\|dffs\[6\]~1400'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "1.100 ns" { lpm_counter:CNT3_rtl_2|dffs[6]~1401 lpm_counter:CNT3_rtl_2|dffs[6]~1400 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 6.900 ns lpm_counter:CNT3_rtl_2\|dffs\[6\]~1346 4 COMB LC54 1 " "Info: 4: + IC(0.000 ns) + CELL(1.100 ns) = 6.900 ns; Loc. = LC54; Fanout = 1; COMB Node = 'lpm_counter:CNT3_rtl_2\|dffs\[6\]~1346'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "1.100 ns" { lpm_counter:CNT3_rtl_2|dffs[6]~1400 lpm_counter:CNT3_rtl_2|dffs[6]~1346 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 8.000 ns lpm_counter:CNT3_rtl_2\|dffs\[6\] 5 REG LC55 67 " "Info: 5: + IC(0.000 ns) + CELL(1.100 ns) = 8.000 ns; Loc. = LC55; Fanout = 67; REG Node = 'lpm_counter:CNT3_rtl_2\|dffs\[6\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "1.100 ns" { lpm_counter:CNT3_rtl_2|dffs[6]~1346 lpm_counter:CNT3_rtl_2|dffs[6] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 78.75 % " "Info: Total cell delay = 6.300 ns ( 78.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 21.25 % " "Info: Total interconnect delay = 1.700 ns ( 21.25 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.000 ns" { lpm_counter:CNT3_rtl_2|dffs[0] lpm_counter:CNT3_rtl_2|dffs[6]~1401 lpm_counter:CNT3_rtl_2|dffs[6]~1400 lpm_counter:CNT3_rtl_2|dffs[6]~1346 lpm_counter:CNT3_rtl_2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:CNT3_rtl_2|dffs[0] lpm_counter:CNT3_rtl_2|dffs[6]~1401 lpm_counter:CNT3_rtl_2|dffs[6]~1400 lpm_counter:CNT3_rtl_2|dffs[6]~1346 lpm_counter:CNT3_rtl_2|dffs[6] } { 0.000ns 1.700ns 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 1.100ns 1.100ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.600 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "" { clk } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns f200hz~reg0 2 REG LC35 67 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC35; Fanout = 67; REG Node = 'f200hz~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "2.000 ns" { clk f200hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(3.100 ns) 8.600 ns lpm_counter:CNT3_rtl_2\|dffs\[6\] 3 REG LC55 67 " "Info: 3: + IC(1.900 ns) + CELL(3.100 ns) = 8.600 ns; Loc. = LC55; Fanout = 67; REG Node = 'lpm_counter:CNT3_rtl_2\|dffs\[6\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "5.000 ns" { f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[6] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 77.91 % " "Info: Total cell delay = 6.700 ns ( 77.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 22.09 % " "Info: Total interconnect delay = 1.900 ns ( 22.09 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[6] } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.600 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "" { clk } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns f200hz~reg0 2 REG LC35 67 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC35; Fanout = 67; REG Node = 'f200hz~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "2.000 ns" { clk f200hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(3.100 ns) 8.600 ns lpm_counter:CNT3_rtl_2\|dffs\[0\] 3 REG LC5 72 " "Info: 3: + IC(1.900 ns) + CELL(3.100 ns) = 8.600 ns; Loc. = LC5; Fanout = 72; REG Node = 'lpm_counter:CNT3_rtl_2\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "5.000 ns" { f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 77.91 % " "Info: Total cell delay = 6.700 ns ( 77.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 22.09 % " "Info: Total interconnect delay = 1.900 ns ( 22.09 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[6] } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.000 ns" { lpm_counter:CNT3_rtl_2|dffs[0] lpm_counter:CNT3_rtl_2|dffs[6]~1401 lpm_counter:CNT3_rtl_2|dffs[6]~1400 lpm_counter:CNT3_rtl_2|dffs[6]~1346 lpm_counter:CNT3_rtl_2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:CNT3_rtl_2|dffs[0] lpm_counter:CNT3_rtl_2|dffs[6]~1401 lpm_counter:CNT3_rtl_2|dffs[6]~1400 lpm_counter:CNT3_rtl_2|dffs[6]~1346 lpm_counter:CNT3_rtl_2|dffs[6] } { 0.000ns 1.700ns 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 1.100ns 1.100ns 1.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[6] } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 lpm_counter:CNT3_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk f1hz f1hz~reg0 10.400 ns register " "Info: tco from clock \"clk\" to destination pin \"f1hz\" through register \"f1hz~reg0\" is 10.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "" { clk } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns f200hz~reg0 2 REG LC35 67 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC35; Fanout = 67; REG Node = 'f200hz~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "2.000 ns" { clk f200hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(3.100 ns) 8.600 ns f1hz~reg0 3 REG LC11 1 " "Info: 3: + IC(1.900 ns) + CELL(3.100 ns) = 8.600 ns; Loc. = LC11; Fanout = 1; REG Node = 'f1hz~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "5.000 ns" { f200hz~reg0 f1hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 77.91 % " "Info: Total cell delay = 6.700 ns ( 77.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 22.09 % " "Info: Total interconnect delay = 1.900 ns ( 22.09 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 f1hz~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 f1hz~reg0 } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.400 ns + Longest register pin " "Info: + Longest register to pin delay is 0.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns f1hz~reg0 1 REG LC11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 1; REG Node = 'f1hz~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "" { f1hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns f1hz 2 PIN PIN_8 0 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns 100.00 % " "Info: Total cell delay = 0.400 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { f1hz~reg0 f1hz } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "8.600 ns" { clk f200hz~reg0 f1hz~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out f200hz~reg0 f1hz~reg0 } { 0.000ns 0.000ns 0.000ns 1.900ns } { 0.000ns 1.600ns 2.000ns 3.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/fdiv/" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { f1hz~reg0 f1hz } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 19:33:22 2006 " "Info: Processing ended: Sat Jul 15 19:33:22 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}