time_auto_and_set.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[0\] register timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[1\] 144.93 MHz 6.9 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 144.93 MHz between source register \"timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[0\]\" and destination register \"timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[1\]\" (period= 6.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns + Longest register register " "Info: + Longest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[0\] 1 REG LC58 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC58; Fanout = 7; REG Node = 'timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 4.500 ns timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[1\] 2 REG LC7 6 " "Info: 2: + IC(1.500 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC7; Fanout = 6; REG Node = 'timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.500 ns" { timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 66.67 % " "Info: Total cell delay = 3.000 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 33.33 % " "Info: Total interconnect delay = 1.500 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.500 ns" { timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } { 0.000ns 1.500ns } { 0.000ns 3.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns SW2 1 CLK PIN_2 20 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_2; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { SW2 } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[1\] 2 REG LC7 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC7; Fanout = 6; REG Node = 'timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "0.600 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { SW2 SW2~out timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns SW2 1 CLK PIN_2 20 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_2; Fanout = 20; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { SW2 } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[0\] 2 REG LC58 7 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC58; Fanout = 7; REG Node = 'timeset:b2v_inst3\|lpm_counter:minute_set1_rtl_7\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "0.600 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { SW2 SW2~out timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { SW2 SW2~out timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { SW2 SW2~out timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.500 ns" { timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } { 0.000ns 1.500ns } { 0.000ns 3.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { SW2 SW2~out timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { SW2 timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { SW2 SW2~out timeset:b2v_inst3|lpm_counter:minute_set1_rtl_7|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO Timepiece_EN CLK 4.700 ns register " "Info: tsu for register \"timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO\" (data pin = \"Timepiece_EN\", clock pin = \"CLK\") is 4.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest pin register " "Info: + Longest pin to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Timepiece_EN 1 PIN PIN_81 69 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 69; PIN Node = 'Timepiece_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { Timepiece_EN } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.000 ns) 4.800 ns timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|LessThan~76 2 COMB LC17 1 " "Info: 2: + IC(1.600 ns) + CELL(3.000 ns) = 4.800 ns; Loc. = LC17; Fanout = 1; COMB Node = 'timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|LessThan~76'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.600 ns" { Timepiece_EN timepiece_main:b2v_inst1|second_counter:b2v_inst2|LessThan~76 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 5.900 ns timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 3 REG LC18 11 " "Info: 3: + IC(0.000 ns) + CELL(1.100 ns) = 5.900 ns; Loc. = LC18; Fanout = 11; REG Node = 'timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "1.100 ns" { timepiece_main:b2v_inst1|second_counter:b2v_inst2|LessThan~76 timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns 72.88 % " "Info: Total cell delay = 4.300 ns ( 72.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 27.12 % " "Info: Total interconnect delay = 1.600 ns ( 27.12 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "5.900 ns" { Timepiece_EN timepiece_main:b2v_inst1|second_counter:b2v_inst2|LessThan~76 timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.900 ns" { Timepiece_EN Timepiece_EN~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|LessThan~76 timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 1.600ns 0.000ns } { 0.000ns 0.200ns 3.000ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { CLK } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 2 REG LC18 11 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC18; Fanout = 11; REG Node = 'timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "0.600 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "5.900 ns" { Timepiece_EN timepiece_main:b2v_inst1|second_counter:b2v_inst2|LessThan~76 timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.900 ns" { Timepiece_EN Timepiece_EN~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|LessThan~76 timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 1.600ns 0.000ns } { 0.000ns 0.200ns 3.000ns 1.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK hour_0\[3\] timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\] 21.500 ns register " "Info: tco from clock \"CLK\" to destination pin \"hour_0\[3\]\" through register \"timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\]\" is 21.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.200 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 14.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { CLK } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 2 REG LC18 11 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC18; Fanout = 11; REG Node = 'timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.000 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(4.500 ns) 9.600 ns timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 3 REG LC2 10 " "Info: 3: + IC(1.500 ns) + CELL(4.500 ns) = 9.600 ns; Loc. = LC2; Fanout = 10; REG Node = 'timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt"