time_auto_and_set.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO " "Info: Detected ripple clock \"timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO\" as buffer" {  } { { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/minute_counter.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO " "Info: Detected ripple clock \"timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO\" as buffer" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\] register timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 125.0 MHz 8.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 125.0 MHz between source register \"timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\]\" and destination register \"timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO\" (period= 8.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns + Longest register register " "Info: + Longest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\] 1 REG LC41 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC41; Fanout = 24; REG Node = 'timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 4.500 ns timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO~154 2 COMB LC42 1 " "Info: 2: + IC(1.500 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC42; Fanout = 1; COMB Node = 'timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO~154'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.500 ns" { timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO~154 } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 5.600 ns timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 3 REG LC43 4 " "Info: 3: + IC(0.000 ns) + CELL(1.100 ns) = 5.600 ns; Loc. = LC43; Fanout = 4; REG Node = 'timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "1.100 ns" { timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO~154 timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns 73.21 % " "Info: Total cell delay = 4.100 ns ( 73.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 26.79 % " "Info: Total interconnect delay = 1.500 ns ( 26.79 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "5.600 ns" { timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO~154 timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO~154 timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } { 0.000ns 1.500ns 0.000ns } { 0.000ns 3.000ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 14.200 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 14.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { CLK } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 2 REG LC18 11 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC18; Fanout = 11; REG Node = 'timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.000 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(4.500 ns) 9.600 ns timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 3 REG LC2 10 " "Info: 3: + IC(1.500 ns) + CELL(4.500 ns) = 9.600 ns; Loc. = LC2; Fanout = 10; REG Node = 'timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "6.000 ns" { timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.100 ns) 14.200 ns timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 4 REG LC43 4 " "Info: 4: + IC(1.500 ns) + CELL(3.100 ns) = 14.200 ns; Loc. = LC43; Fanout = 4; REG Node = 'timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.600 ns" { timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns 78.87 % " "Info: Total cell delay = 11.200 ns ( 78.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 21.13 % " "Info: Total interconnect delay = 3.000 ns ( 21.13 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "14.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.500ns 1.500ns } { 0.000ns 1.600ns 2.000ns 4.500ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.200 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 14.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { CLK } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 2 REG LC18 11 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC18; Fanout = 11; REG Node = 'timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "2.000 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(4.500 ns) 9.600 ns timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 3 REG LC2 10 " "Info: 3: + IC(1.500 ns) + CELL(4.500 ns) = 9.600 ns; Loc. = LC2; Fanout = 10; REG Node = 'timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "6.000 ns" { timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.100 ns) 14.200 ns timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\] 4 REG LC41 24 " "Info: 4: + IC(1.500 ns) + CELL(3.100 ns) = 14.200 ns; Loc. = LC41; Fanout = 24; REG Node = 'timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.600 ns" { timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns 78.87 % " "Info: Total cell delay = 11.200 ns ( 78.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 21.13 % " "Info: Total interconnect delay = 3.000 ns ( 21.13 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "14.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns 1.500ns 1.500ns } { 0.000ns 1.600ns 2.000ns 4.500ns 3.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "14.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.500ns 1.500ns } { 0.000ns 1.600ns 2.000ns 4.500ns 3.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "14.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns 1.500ns 1.500ns } { 0.000ns 1.600ns 2.000ns 4.500ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/hour_counter.v" 4 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "5.600 ns" { timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO~154 timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO~154 timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } { 0.000ns 1.500ns 0.000ns } { 0.000ns 3.000ns 1.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "14.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.500ns 1.500ns } { 0.000ns 1.600ns 2.000ns 4.500ns 3.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "14.200 ns" { CLK timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.200 ns" { CLK CLK~out timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns 1.500ns 1.500ns } { 0.000ns 1.600ns 2.000ns 4.500ns 3.100ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register timeset:b2v_inst3\|disp_drive\[0\] register timeset:b2v_inst3\|disp_drive\[1\] 140.85 MHz 7.1 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 140.85 MHz between source register \"timeset:b2v_inst3\|disp_drive\[0\]\" and destination register \"timeset:b2v_inst3\|disp_drive\[1\]\" (period= 7.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register register " "Info: + Longest register to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timeset:b2v_inst3\|disp_drive\[0\] 1 REG LC49 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC49; Fanout = 26; REG Node = 'timeset:b2v_inst3\|disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(3.000 ns) 4.700 ns timeset:b2v_inst3\|disp_drive\[1\] 2 REG LC53 26 " "Info: 2: + IC(1.700 ns) + CELL(3.000 ns) = 4.700 ns; Loc. = LC53; Fanout = 26; REG Node = 'timeset:b2v_inst3\|disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { timeset:b2v_inst3|disp_drive[0] timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 63.83 % " "Info: Total cell delay = 3.000 ns ( 63.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 36.17 % " "Info: Total interconnect delay = 1.700 ns ( 36.17 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { timeset:b2v_inst3|disp_drive[0] timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { timeset:b2v_inst3|disp_drive[0] timeset:b2v_inst3|disp_drive[1] } { 0.000ns 1.700ns } { 0.000ns 3.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 4.700 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { SW1 } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.100 ns) 4.700 ns timeset:b2v_inst3\|disp_drive\[1\] 2 REG LC53 26 " "Info: 2: + IC(1.400 ns) + CELL(3.100 ns) = 4.700 ns; Loc. = LC53; Fanout = 26; REG Node = 'timeset:b2v_inst3\|disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.500 ns" { SW1 timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns 70.21 % " "Info: Total cell delay = 3.300 ns ( 70.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 29.79 % " "Info: Total interconnect delay = 1.400 ns ( 29.79 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { SW1 timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { SW1 SW1~out timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 4.700 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 3; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "" { SW1 } "NODE_NAME" } "" } } { "time_auto_and_set.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/time_auto_and_set.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.100 ns) 4.700 ns timeset:b2v_inst3\|disp_drive\[0\] 2 REG LC49 26 " "Info: 2: + IC(1.400 ns) + CELL(3.100 ns) = 4.700 ns; Loc. = LC49; Fanout = 26; REG Node = 'timeset:b2v_inst3\|disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.500 ns" { SW1 timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns 70.21 % " "Info: Total cell delay = 3.300 ns ( 70.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 29.79 % " "Info: Total interconnect delay = 1.400 ns ( 29.79 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { SW1 timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { SW1 SW1~out timeset:b2v_inst3|disp_drive[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { SW1 timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { SW1 SW1~out timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { SW1 timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { SW1 SW1~out timeset:b2v_inst3|disp_drive[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/timeset.v" 15 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { timeset:b2v_inst3|disp_drive[0] timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { timeset:b2v_inst3|disp_drive[0] timeset:b2v_inst3|disp_drive[1] } { 0.000ns 1.700ns } { 0.000ns 3.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { SW1 timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { SW1 SW1~out timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set_cmp.qrpt" Compiler "time_auto_and_set" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/db/time_auto_and_set.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_auto_and_set/" "" "4.700 ns" { SW1 timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { SW1 SW1~out timeset:b2v_inst3|disp_drive[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.100ns } } }  } 0}