time_auto_and_set.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

; Worst-case th                ; N/A   ; None          ; 11.100 ns                        ; Timepiece_EN                                                                             ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO                                         ;            ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 125.00 MHz ( period = 8.000 ns ) ; timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data0_rtl_8|dffs[1] ; timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data1_rtl_10|dffs[2] ; CLK        ; CLK      ; 0            ;
; Clock Setup: 'SW1'           ; N/A   ; None          ; 140.85 MHz ( period = 7.100 ns ) ; timeset:b2v_inst3|disp_drive[1]                                                          ; timeset:b2v_inst3|disp_drive[0]                                                           ; SW1        ; SW1      ; 0            ;
; Clock Setup: 'SW2'           ; N/A   ; None          ; 144.93 MHz ( period = 6.900 ns ) ; timeset:b2v_inst3|lpm_counter:hour_set1_rtl_3|dffs[1]                                    ; timeset:b2v_inst3|lpm_counter:hour_set1_rtl_3|dffs[0]                                     ; SW2        ; SW2      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                          ;                                                                                           ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128SLC84-6     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW1             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW2             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                           ;
+-------+----------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                                                                                      ; To                                                                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+-------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 125.00 MHz ( period = 8.000 ns ) ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3]       ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO                                         ; CLK        ; CLK      ; None                        ; None                      ; 5.600 ns                ;
; N/A   ; 125.00 MHz ( period = 8.000 ns ) ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[1]       ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_2|dffs[0]       ; CLK        ; CLK      ; None                        ; None                      ; 5.600 ns                ;
; N/A   ; 125.00 MHz ( period = 8.000 ns ) ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3]       ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_2|dffs[0]       ; CLK        ; CLK      ; None                        ; None                      ; 5.600 ns                ;
; N/A   ; 125.00 MHz ( period = 8.000 ns ) ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[1]       ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[2]       ; CLK        ; CLK      ; None                        ; None                      ; 5.600 ns                ;
; N/A   ; 125.00 MHz ( period = 8.000 ns ) ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[3]       ; timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[2]       ; CLK        ; CLK      ; None                        ; None                      ; 5.600 ns                ;