pwm.tan.qmsg

一个在CPLD

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:q_rtl_0\|dffs\[11\] register pwm_buf 47.62 MHz 21.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 47.62 MHz between source register \"lpm_counter:q_rtl_0\|dffs\[11\]\" and destination register \"pwm_buf\" (period= 21.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest register register " "Info: + Longest register to register delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:q_rtl_0\|dffs\[11\] 1 REG LC121 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC121; Fanout = 6; REG Node = 'lpm_counter:q_rtl_0\|dffs\[11\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { lpm_counter:q_rtl_0|dffs[11] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns LessThan~413 2 COMB SEXP115 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP115; Fanout = 1; COMB Node = 'LessThan~413'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "10.000 ns" { lpm_counter:q_rtl_0|dffs[11] LessThan~413 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 16.000 ns pwm_buf 3 REG LC128 1 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "6.000 ns" { LessThan~413 pwm_buf } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 87.50 % " "Info: Total cell delay = 14.000 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 12.50 % " "Info: Total interconnect delay = 2.000 ns ( 12.50 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "16.000 ns" { lpm_counter:q_rtl_0|dffs[11] LessThan~413 pwm_buf } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "16.000 ns" { lpm_counter:q_rtl_0|dffs[11] LessThan~413 pwm_buf } { 0.000ns 2.000ns 0.000ns } { 0.000ns 8.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 21 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { clk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pwm_buf 2 REG LC128 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "0.000 ns" { clk pwm_buf } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_buf } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 21 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { clk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:q_rtl_0\|dffs\[11\] 2 REG LC121 6 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC121; Fanout = 6; REG Node = 'lpm_counter:q_rtl_0\|dffs\[11\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "0.000 ns" { clk lpm_counter:q_rtl_0|dffs[11] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk lpm_counter:q_rtl_0|dffs[11] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:q_rtl_0|dffs[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_buf } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk lpm_counter:q_rtl_0|dffs[11] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:q_rtl_0|dffs[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "16.000 ns" { lpm_counter:q_rtl_0|dffs[11] LessThan~413 pwm_buf } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "16.000 ns" { lpm_counter:q_rtl_0|dffs[11] LessThan~413 pwm_buf } { 0.000ns 2.000ns 0.000ns } { 0.000ns 8.000ns 6.000ns } } } { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_buf } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk lpm_counter:q_rtl_0|dffs[11] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:q_rtl_0|dffs[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "pwm_cnt\[1\] key\[0\] clk 11.000 ns register " "Info: tsu for register \"pwm_cnt\[1\]\" (data pin = \"key\[0\]\", clock pin = \"clk\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns key\[0\] 1 PIN PIN_33 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 7; PIN Node = 'key\[0\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { key[0] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns pwm_cnt\[1\] 2 REG LC7 8 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt\[1\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "8.000 ns" { key[0] pwm_cnt[1] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "10.000 ns" { key[0] pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { key[0] key[0]~out pwm_cnt[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 21 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { clk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pwm_cnt\[1\] 2 REG LC7 8 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt\[1\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "0.000 ns" { clk pwm_cnt[1] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_cnt[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "10.000 ns" { key[0] pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { key[0] key[0]~out pwm_cnt[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_cnt[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk pwm_out pwm_buf 8.000 ns register " "Info: tco from clock \"clk\" to destination pin \"pwm_out\" through register \"pwm_buf\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 21 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { clk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pwm_buf 2 REG LC128 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "0.000 ns" { clk pwm_buf } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_buf } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm_buf 1 REG LC128 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { pwm_buf } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns pwm_out 2 PIN PIN_81 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'pwm_out'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "4.000 ns" { pwm_buf pwm_out } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "4.000 ns" { pwm_buf pwm_out } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { pwm_buf pwm_out } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_buf } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "4.000 ns" { pwm_buf pwm_out } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { pwm_buf pwm_out } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "pwm_cnt\[1\] key\[0\] clk -3.000 ns register " "Info: th for register \"pwm_cnt\[1\]\" (data pin = \"key\[0\]\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 21 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { clk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pwm_cnt\[1\] 2 REG LC7 8 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt\[1\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "0.000 ns" { clk pwm_cnt[1] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_cnt[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns key\[0\] 1 PIN PIN_33 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 7; PIN Node = 'key\[0\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "" { key[0] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns pwm_cnt\[1\] 2 REG LC7 8 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt\[1\]'" {  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "8.000 ns" { key[0] pwm_cnt[1] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "10.000 ns" { key[0] pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { key[0] key[0]~out pwm_cnt[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "3.000 ns" { clk pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pwm_cnt[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" "" { Report "H:/changzhou/edadiy/实验程序/PWM/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "H:/changzhou/edadiy/实验程序/PWM/db/PWM.quartus_db" { Floorplan "H:/changzhou/edadiy/实验程序/PWM/" "" "10.000 ns" { key[0] pwm_cnt[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { key[0] key[0]~out pwm_cnt[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 07 20:52:46 2006 " "Info: Processing ended: Fri Apr 07 20:52:46 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}