6713emiftofpgatopci.vhd

这个是完整的一套从6713的emif到fpga的双口ram

----------------------------------------------------------------------------------
-- Company: ioe
-- Engineer: dingke
-- 
-- Create Date:    01:00:14 04/05/2008 
-- Design Name:    dpram for dsp6713 communication with the host(pc)
-- Module Name:    vhdl1 - Behavioral 
-- Project Name:   dsp-fpga-dpram-pci-host
-- Target Devices: 
-- Tool versions: 
-- Description:  for 6713dsp's emif to read and write to the ram inside the fpga!
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity vhdl1 is
	generic (
		-- EMIF port / Port A
		NumberOfDataBits 	: integer := 16;	-- 8-bit EMIF
		NumberOfAddrBits 	: integer := 9;	-- 9 Address lines for Block RAM
		-- System Port / Port B
		NumberOfSysDataBits : integer := 16;
		NumberOfSysAddrBits : integer := 9
		--you can change the number of the address lines here without modificaions in the whole code.
	);
	 port (
	     
	     dsprst: in std_logic;
		  flashrst: out std_logic;
        -- EMIF side
        tardy: out std_logic;
		  EmifClk		: in std_logic;
        --EmifRst		: in std_logic;
        EmifAddr	: in std_logic_vector (NumberOfAddrBits-1 downto 0);
        EmifData	: inout std_logic_vector (NumberOfDataBits-1 downto 0);
        EmifSoe		: in std_logic;
        EmifCe		: in std_logic;
        EmifSwe		: in std_logic;
        EmifSads	: in std_logic;
        --EmifBe		: in std_logic_vector (((NumberOfDataBits/8)-1) downto 0); not used here!
          -- Internal or system side
		  lhold: in std_logic;   ---request for the local bus;
		  lholda: out std_logic;   ---grant the pci for the bus;
		  ads: in std_logic;
		  blast: in std_logic;
		  lbe1:in std_logic;   ---16bit pci use
		  --lbe0: in std_logic;  ---8bit pci use!!
		  lwr: in std_logic;----read or write signal
        ready: out std_logic; 
		  pciClk		: in std_logic;---50Mhz
        ---pciRst		: in std_logic;---connected to the lint?
        laddr  : in std_logic_vector (NumberOfSysAddrBits-1 downto 1);    ---0 for 32bit,1 for 16 bit ,2 for 8bit;  -- Address can be different width.
        ldata	: Inout std_logic_vector (NumberOfSysDataBits-1 downto 0); -- Data can be different width.
		  ---pci's pullup or pulldown for the fpga's chaos
		  bterm: out std_logic;
		  --lserr:out std_logic;
		  ---breqo:out std_logic;
		  breqi:out std_logic;
		  wait1:out std_logic;
		  --lreset:out std_logic;
		  --eot:out std_logic;
		  lint:out std_logic;
		  dreqo:out std_logic;
		  --dacko:out std_logic;
		  ccs:out std_logic;
		  bigend:out std_logic
		  );


end vhdl1;

architecture Behavioral of vhdl1 is

--component instantiation--

component dpram1
port (
----for emif
addra: IN std_logic_VECTOR(NumberOfAddrBits-1 downto 0);
clka: IN std_logic;
dina: IN std_logic_VECTOR(NumberOfDataBits-1 downto 0);
douta: OUT std_logic_VECTOR(NumberOfDataBits-1 downto 0);
ena: IN std_logic;
wea: IN std_logic;
----for pci;	
addrb: IN std_logic_VECTOR(NumberOfSysAddrBits-1 downto 0);
clkb: IN std_logic;
dinb: IN std_logic_VECTOR(NumberOfSysDataBits-1 downto 0);
doutb: OUT std_logic_VECTOR(NumberOfSysDataBits-1 downto 0);
enb: IN std_logic;
web: IN std_logic
		);
	
  end component;

signal   clka : std_logic;
signal	dina :  std_logic_vector (NumberOfDataBits-1 downto 0);
signal   addra : std_logic_vector (NumberOfAddrBits-1 downto 0);
signal	ena :   std_logic;
signal	wea :   std_logic;
signal	douta : std_logic_vector (NumberOfDataBits-1 downto 0);

signal   clkb : std_logic;
signal	dinb :  std_logic_vector (NumberOfSysDataBits-1 downto 0);
signal   addrb : std_logic_vector (NumberOfSysAddrBits-1 downto 0);
signal	enb :   std_logic;
signal	web :   std_logic;
signal	doutb : std_logic_vector (NumberOfSysDataBits -1 downto 0);
signal	pciaddr : std_logic_vector (NumberOfSysAddrBits-1 downto 0);
--signal	rd : std_logic_vector (1 downto 0);
--signal	ldata1 : std_logic_vector (NumberOfSysDataBits -1 downto 0)	;


begin 

----port map to the dpram1
	u1: dpram1 port map (clka=>clka,
	                dina=>dina,
                addra=>addra,
                ena=>ena,
                wea=>wea,
                douta=>douta,
					 clkb=>clkb,
	                dinb=>dinb,
                addrb=>addrb,
                enb=>enb,
                web=>web,
                doutb=>doutb);
					 

tardy<='1'; -----forbid the dpram to insert the wait status. that is to say the dpram is alwayse ready!

ready<='0'; ----the same as the above.

        bterm<='1';
		  --lserr<='1';
		  --breqo<='1';
		  breqi<='0';
		  wait1<='1';
		  --lreset<='1';
		  --eot<='1';
		  lint<='1';
		  dreqo<='1';
		  --dacko<='1';
		  ccs<='1';
		  bigend<='1';

clka<=EmifClk;---portA clock;

clkb<=pciClk;----portB clock!

flashrst<=dsprst; 

----dsp's emif(external memory interface) access to the dpram of fpga!
emiftoram: process(EmifClk,EmifCe, EmifAddr, EmifSoe, EmifSwe, EmifSads) ----asy access.

begin

  if (EmifClk'event and EmifClk='1') then 

	 if (EmifCe='0') then ena<='1';  addra<=EmifAddr; 

   if (EmifSoe='0') then  wea<='0';   ---read process; 
	
	if (EmifSads='0') then EmifData<=douta; 
  
   else  EmifData<="ZZZZZZZZZZZZZZZZ";
	
	end if; 
	
	end if;
	
	if (EmifSoe='1') then   ---write process;
	
	if (EmifSwe='0') then wea<='1'; dina<=EmifData;
		  
		  else wea<='0'; 
	
	end if;
	
	end if; 
	
	else ena<='0'; 
	
	EmifData<="ZZZZZZZZZZZZZZZZ";  ---in fpga design, the out port or inout port should be bufferd, especially which is add on the bus.
	                               ---so it doesn't pull down the bus!
   
	 end if; 

	end if;

end process;

----host(external memory interface) access to the dpram of fpga through pci9054!

process(pciClk,ads)

begin

pciaddr(0)<=lbe1;

FOR i in  1 to (NumberOfSysAddrBits-1) loop ----get the real address

pciaddr(i)<=laddr(i);  end loop;

if (pciClk'event and pciClk='1') then 

    if lhold='1' then lholda<='1'; enb<='1';else lholda<='0';enb<='0'; end if;  ----enable the dpram!

end if;

   if ads='0' then addrb<=pciaddr; end if;---validate and latch the address
	
	--don't put it in the clk to match the dpram timing. 

end process;




--web<='1';dinb<=ldata when lwr='1' and  blast='0' else (others=>'Z');---pci write

pcitoram: process(pciClk)  ----non-burst cycle for the 16 bit local bus

begin

if (pciClk'event and pciClk='0') then 
	 
	 if (lwr='1' and  blast='0') then web<='1'; dinb<=ldata; 
	 
	 else web<='0';
	 
 end if;
	 
	 end if;
	 
	-- if lwr='0' then
	 
	-- if blast='0' then  web<='0'; ldata<=doutb; 
	 
	 --     else ldata<="ZZZZZZZZZZZZZZZZ"; end if;
	 
	 --end if;
	 
end process;

ldata<=doutb when lwr='0' and  blast='0' else (others=>'Z'); ----pci read

--process(pciClk)  ----no use!
--begin
--if (pciClk'event and pciClk='1') then 
	 
--	 ldata<=ldata1; 
	 
--	 end if;
	 
	-- end process;

end Behavioral;