ad_s_machine.vhd

用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制

library ieee;
use ieee.std_logic_1164.all;

entity ad_s_machine is
  port (clk : in std_logic;
        eoc : in std_logic;
        data : in std_logic_vector(7 downto 0);
        ale  : out std_logic;
        start : out std_logic; 
        oe  : out std_logic;
        lock0  : out std_logic;
        adda : out std_logic;
        c_state : out std_logic_vector( 4 downto 0 );
        q : out std_logic_vector(7 downto 0));
end  ad_s_machine;

architecture behav of ad_s_machine is

  signal current_state,next_state : std_logic_vector( 4 downto 0 );

  constant s0 : std_logic_vector( 4 downto 0 ) := "00000";
  constant s1 : std_logic_vector( 4 downto 0 ) := "11000";
  constant s2 : std_logic_vector( 4 downto 0 ) := "00001";
  constant s3 : std_logic_vector( 4 downto 0 ) := "00100";
  constant s4 : std_logic_vector( 4 downto 0 ) := "00110";
  
  signal lock :std_logic;
  signal regq : std_logic_vector(7 downto 0);

begin
  start <= current_state(4);
  ale   <= current_state(3);
  oe    <= current_state(2);
  lock  <= current_state(1);
  c_state <= current_state;
  q<=regq;lock0<=lock;
  adda<='0';

  reg : process(clk)
        begin
          if clk'event and clk='1' then current_state<=next_state;
          end if;
        end process;

  com : process(current_state,eoc)
        begin
          case current_state is
              when s0 => next_state<=s1;
              when s1 => next_state<=s2;
              when s2 => if eoc='1' then next_state<=s3;
                          else next_state<=s2;
                         end if;
              when s3 => next_state<=s4;
              when s4 => next_state<=s0; 
              when others => next_state<=s0;       
           end case;
         end process;

  latch :process(lock)
         begin
         if lock'event and lock='1' then regq<=data;
          end if;
        end process;
         
end behav;