ad_s_machine.tan.qmsg

用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制

{ "Info" "ITDB_TH_RESULT" "regq\[2\] data\[2\] clk 1.500 ns register " "Info: th for register \"regq\[2\]\" (data pin = \"data\[2\]\", clock pin = \"clk\") is 1.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.359 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad_s_machine.vhd" "" { Text "E:/practise/ad_s_machine/ad_s_machine.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.935 ns) 3.470 ns current_state\[1\] 2 REG LC_X7_Y16_N8 14 " "Info: 2: + IC(1.066 ns) + CELL(0.935 ns) = 3.470 ns; Loc. = LC_X7_Y16_N8; Fanout = 14; REG Node = 'current_state\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.001 ns" { clk current_state[1] } "NODE_NAME" } } { "ad_s_machine.vhd" "" { Text "E:/practise/ad_s_machine/ad_s_machine.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.178 ns) + CELL(0.711 ns) 8.359 ns regq\[2\] 3 REG LC_X8_Y22_N2 1 " "Info: 3: + IC(4.178 ns) + CELL(0.711 ns) = 8.359 ns; Loc. = LC_X8_Y22_N2; Fanout = 1; REG Node = 'regq\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.889 ns" { current_state[1] regq[2] } "NODE_NAME" } } { "ad_s_machine.vhd" "" { Text "E:/practise/ad_s_machine/ad_s_machine.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.27 % ) " "Info: Total cell delay = 3.115 ns ( 37.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.244 ns ( 62.73 % ) " "Info: Total interconnect delay = 5.244 ns ( 62.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.359 ns" { clk current_state[1] regq[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.359 ns" { clk clk~out0 current_state[1] regq[2] } { 0.000ns 0.000ns 1.066ns 4.178ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ad_s_machine.vhd" "" { Text "E:/practise/ad_s_machine/ad_s_machine.vhd" 61 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.874 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns data\[2\] 1 PIN PIN_15 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_15; Fanout = 1; PIN Node = 'data\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data[2] } "NODE_NAME" } } { "ad_s_machine.vhd" "" { Text "E:/practise/ad_s_machine/ad_s_machine.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.290 ns) + CELL(0.115 ns) 6.874 ns regq\[2\] 2 REG LC_X8_Y22_N2 1 " "Info: 2: + IC(5.290 ns) + CELL(0.115 ns) = 6.874 ns; Loc. = LC_X8_Y22_N2; Fanout = 1; REG Node = 'regq\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.405 ns" { data[2] regq[2] } "NODE_NAME" } } { "ad_s_machine.vhd" "" { Text "E:/practise/ad_s_machine/ad_s_machine.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 23.04 % ) " "Info: Total cell delay = 1.584 ns ( 23.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.290 ns ( 76.96 % ) " "Info: Total interconnect delay = 5.290 ns ( 76.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.874 ns" { data[2] regq[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.874 ns" { data[2] data[2]~out0 regq[2] } { 0.000ns 0.000ns 5.290ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.359 ns" { clk current_state[1] regq[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.359 ns" { clk clk~out0 current_state[1] regq[2] } { 0.000ns 0.000ns 1.066ns 4.178ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.874 ns" { data[2] regq[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.874 ns" { data[2] data[2]~out0 regq[2] } { 0.000ns 0.000ns 5.290ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 28 12:17:06 2006 " "Info: Processing ended: Sat Oct 28 12:17:06 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}