ad_s_machine.hier_info

用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制

|ad_s_machine
clk => current_state[0].CLK
clk => current_state[1].CLK
clk => current_state[2].CLK
clk => current_state[3].CLK
clk => current_state[4].CLK
eoc => Mux2.IN31
eoc => Mux4.IN31
data[0] => regq[0].DATAIN
data[1] => regq[1].DATAIN
data[2] => regq[2].DATAIN
data[3] => regq[3].DATAIN
data[4] => regq[4].DATAIN
data[5] => regq[5].DATAIN
data[6] => regq[6].DATAIN
data[7] => regq[7].DATAIN
ale <= current_state[3].DB_MAX_OUTPUT_PORT_TYPE
start <= current_state[4].DB_MAX_OUTPUT_PORT_TYPE
oe <= current_state[2].DB_MAX_OUTPUT_PORT_TYPE
lock0 <= current_state[1].DB_MAX_OUTPUT_PORT_TYPE
adda <= <GND>
c_state[0] <= current_state[0].DB_MAX_OUTPUT_PORT_TYPE
c_state[1] <= current_state[1].DB_MAX_OUTPUT_PORT_TYPE
c_state[2] <= current_state[2].DB_MAX_OUTPUT_PORT_TYPE
c_state[3] <= current_state[3].DB_MAX_OUTPUT_PORT_TYPE
c_state[4] <= current_state[4].DB_MAX_OUTPUT_PORT_TYPE
q[0] <= regq[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= regq[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= regq[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= regq[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= regq[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= regq[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= regq[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= regq[7].DB_MAX_OUTPUT_PORT_TYPE