ad_s_machine.map.rpt

用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                           ;
+----------------------------------+-----------------+-----------------+-------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path              ;
+----------------------------------+-----------------+-----------------+-------------------------------------------+
; ad_s_machine.vhd                 ; yes             ; User VHDL File  ; E:/practise/ad_s_machine/ad_s_machine.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------+


+----------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                    ;
+---------------------------------------------+------------------+
; Resource                                    ; Usage            ;
+---------------------------------------------+------------------+
; Total logic elements                        ; 14               ;
;     -- Combinational with no register       ; 2                ;
;     -- Register only                        ; 8                ;
;     -- Combinational with a register        ; 4                ;
;                                             ;                  ;
; Logic element usage by number of LUT inputs ;                  ;
;     -- 4 input functions                    ; 4                ;
;     -- 3 input functions                    ; 0                ;
;     -- 2 input functions                    ; 2                ;
;     -- 1 input functions                    ; 0                ;
;     -- 0 input functions                    ; 0                ;
;         -- Combinational cells for routing  ; 0                ;
;                                             ;                  ;
; Logic elements by mode                      ;                  ;
;     -- normal mode                          ; 14               ;
;     -- arithmetic mode                      ; 0                ;
;     -- qfbk mode                            ; 0                ;
;     -- register cascade mode                ; 0                ;
;     -- synchronous clear/load mode          ; 0                ;
;     -- asynchronous clear/load mode         ; 0                ;
;                                             ;                  ;
; Total registers                             ; 12               ;
; I/O pins                                    ; 28               ;
; Maximum fan-out node                        ; current_state[1] ;
; Maximum fan-out                             ; 14               ;
; Total fan-out                               ; 57               ;
; Average fan-out                             ; 1.36             ;
+---------------------------------------------+------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |ad_s_machine              ; 14 (14)     ; 12           ; 0           ; 0    ; 28   ; 0            ; 2 (2)        ; 8 (8)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |ad_s_machine       ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 12    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; Yes        ; |ad_s_machine|current_state[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Oct 28 12:16:39 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ad_s_machine -c ad_s_machine
Info: Found 2 design units, including 1 entities, in source file ad_s_machine.vhd
    Info: Found design unit 1: ad_s_machine-behav
    Info: Found entity 1: ad_s_machine
Info: Elaborating entity "ad_s_machine" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info: Duplicate register "current_state[4]" merged to single register "current_state[3]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "adda" stuck at GND
Info: Implemented 42 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 18 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Oct 28 12:16:42 2006
    Info: Elapsed time: 00:00:04