ad_s_machine.tan.rpt

用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制

; N/A   ; None         ; -1.448 ns  ; data[2] ; regq[2]          ; clk      ;
+-------+--------------+------------+---------+------------------+----------+


+--------------------------------------------------------------------------------+
; tco                                                                            ;
+-------+--------------+------------+------------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To         ; From Clock ;
+-------+--------------+------------+------------------+------------+------------+
; N/A   ; None         ; 16.313 ns  ; regq[2]          ; q[2]       ; clk        ;
; N/A   ; None         ; 15.703 ns  ; regq[7]          ; q[7]       ; clk        ;
; N/A   ; None         ; 15.627 ns  ; regq[3]          ; q[3]       ; clk        ;
; N/A   ; None         ; 15.618 ns  ; regq[6]          ; q[6]       ; clk        ;
; N/A   ; None         ; 15.389 ns  ; regq[4]          ; q[4]       ; clk        ;
; N/A   ; None         ; 14.554 ns  ; regq[0]          ; q[0]       ; clk        ;
; N/A   ; None         ; 14.208 ns  ; regq[1]          ; q[1]       ; clk        ;
; N/A   ; None         ; 13.397 ns  ; current_state[2] ; oe         ; clk        ;
; N/A   ; None         ; 12.488 ns  ; regq[5]          ; q[5]       ; clk        ;
; N/A   ; None         ; 12.144 ns  ; current_state[3] ; c_state[4] ; clk        ;
; N/A   ; None         ; 12.144 ns  ; current_state[3] ; c_state[3] ; clk        ;
; N/A   ; None         ; 12.099 ns  ; current_state[2] ; c_state[2] ; clk        ;
; N/A   ; None         ; 11.296 ns  ; current_state[3] ; start      ; clk        ;
; N/A   ; None         ; 11.296 ns  ; current_state[3] ; ale        ; clk        ;
; N/A   ; None         ; 8.230 ns   ; current_state[1] ; c_state[1] ; clk        ;
; N/A   ; None         ; 8.220 ns   ; current_state[1] ; lock0      ; clk        ;
; N/A   ; None         ; 7.326 ns   ; current_state[0] ; c_state[0] ; clk        ;
+-------+--------------+------------+------------------+------------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+---------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To               ; To Clock ;
+---------------+-------------+-----------+---------+------------------+----------+
; N/A           ; None        ; 1.500 ns  ; data[2] ; regq[2]          ; clk      ;
; N/A           ; None        ; 0.591 ns  ; data[6] ; regq[6]          ; clk      ;
; N/A           ; None        ; 0.575 ns  ; data[3] ; regq[3]          ; clk      ;
; N/A           ; None        ; 0.483 ns  ; data[4] ; regq[4]          ; clk      ;
; N/A           ; None        ; 0.412 ns  ; data[7] ; regq[7]          ; clk      ;
; N/A           ; None        ; -0.599 ns ; data[1] ; regq[1]          ; clk      ;
; N/A           ; None        ; -0.727 ns ; data[0] ; regq[0]          ; clk      ;
; N/A           ; None        ; -2.290 ns ; data[5] ; regq[5]          ; clk      ;
; N/A           ; None        ; -5.517 ns ; eoc     ; current_state[2] ; clk      ;
; N/A           ; None        ; -5.519 ns ; eoc     ; current_state[0] ; clk      ;
+---------------+-------------+-----------+---------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Oct 28 12:17:05 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ad_s_machine -c ad_s_machine --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state[1]" as buffer
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "current_state[1]" and destination register "current_state[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.385 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y16_N8; Fanout = 14; REG Node = 'current_state[1]'
            Info: 2: + IC(0.602 ns) + CELL(0.292 ns) = 0.894 ns; Loc. = LC_X7_Y16_N0; Fanout = 1; COMB Node = 'Mux2~85'
            Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 1.385 ns; Loc. = LC_X7_Y16_N1; Fanout = 6; REG Node = 'current_state[2]'
            Info: Total cell delay = 0.601 ns ( 43.39 % )
            Info: Total interconnect delay = 0.784 ns ( 56.61 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X7_Y16_N1; Fanout = 6; REG Node = 'current_state[2]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
            Info: - Longest clock path from clock "clk" to source register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X7_Y16_N8; Fanout = 14; REG Node = 'current_state[1]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state[0]" (data pin = "eoc", clock pin = "clk") is 5.571 ns
    Info: + Longest pin to register delay is 8.780 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 2; PIN Node = 'eoc'
        Info: 2: + IC(6.573 ns) + CELL(0.738 ns) = 8.780 ns; Loc. = LC_X7_Y16_N4; Fanout = 5; REG Node = 'current_state[0]'
        Info: Total cell delay = 2.207 ns ( 25.14 % )
        Info: Total interconnect delay = 6.573 ns ( 74.86 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.246 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X7_Y16_N4; Fanout = 5; REG Node = 'current_state[0]'
        Info: Total cell delay = 2.180 ns ( 67.16 % )
        Info: Total interconnect delay = 1.066 ns ( 32.84 % )
Info: tco from clock "clk" to destination pin "q[2]" through register "regq[2]" is 16.313 ns
    Info: + Longest clock path from clock "clk" to source register is 8.359 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.066 ns) + CELL(0.935 ns) = 3.470 ns; Loc. = LC_X7_Y16_N8; Fanout = 14; REG Node = 'current_state[1]'
        Info: 3: + IC(4.178 ns) + CELL(0.711 ns) = 8.359 ns; Loc. = LC_X8_Y22_N2; Fanout = 1; REG Node = 'regq[2]'
        Info: Total cell delay = 3.115 ns ( 37.27 % )
        Info: Total interconnect delay = 5.244 ns ( 62.73 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 7.730 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y22_N2; Fanout = 1; REG Node = 'regq[2]'
        Info: 2: + IC(5.606 ns) + CELL(2.124 ns) = 7.730 ns; Loc. = PIN_163; Fanout = 0; PIN Node = 'q[2]'
        Info: Total cell delay = 2.124 ns ( 27.48 % )
        Info: Total interconnect delay = 5.606 ns ( 72.52 % )
Info: th for register "regq[2]" (data pin = "data[2]", clock pin = "clk") is 1.500 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.359 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.066 ns) + CELL(0.935 ns) = 3.470 ns; Loc. = LC_X7_Y16_N8; Fanout = 14; REG Node = 'current_state[1]'
        Info: 3: + IC(4.178 ns) + CELL(0.711 ns) = 8.359 ns; Loc. = LC_X8_Y22_N2; Fanout = 1; REG Node = 'regq[2]'
        Info: Total cell delay = 3.115 ns ( 37.27 % )
        Info: Total interconnect delay = 5.244 ns ( 62.73 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.874 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_15; Fanout = 1; PIN Node = 'data[2]'
        Info: 2: + IC(5.290 ns) + CELL(0.115 ns) = 6.874 ns; Loc. = LC_X8_Y22_N2; Fanout = 1; REG Node = 'regq[2]'
        Info: Total cell delay = 1.584 ns ( 23.04 % )
        Info: Total interconnect delay = 5.290 ns ( 76.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Oct 28 12:17:06 2006
    Info: Elapsed time: 00:00:03