📄 ad_s_machine.tan.rpt
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Timing Analyzer report for ad_s_machine
Sat Oct 28 12:17:07 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.571 ns ; eoc ; current_state[0] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 16.313 ns ; regq[2] ; q[2] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 1.500 ns ; data[2] ; regq[2] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[1] ; current_state[2] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[1] ; current_state[2] ; clk ; clk ; None ; None ; 1.385 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[1] ; current_state[0] ; clk ; clk ; None ; None ; 1.383 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[2] ; current_state[3] ; clk ; clk ; None ; None ; 1.292 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[2] ; current_state[1] ; clk ; clk ; None ; None ; 1.291 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[2] ; current_state[2] ; clk ; clk ; None ; None ; 1.247 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[3] ; current_state[2] ; clk ; clk ; None ; None ; 1.173 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[0] ; current_state[3] ; clk ; clk ; None ; None ; 1.170 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[0] ; current_state[1] ; clk ; clk ; None ; None ; 1.167 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[0] ; current_state[2] ; clk ; clk ; None ; None ; 1.166 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[3] ; current_state[0] ; clk ; clk ; None ; None ; 1.154 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[2] ; current_state[0] ; clk ; clk ; None ; None ; 1.146 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[1] ; current_state[1] ; clk ; clk ; None ; None ; 1.077 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[1] ; current_state[3] ; clk ; clk ; None ; None ; 1.076 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[0] ; current_state[0] ; clk ; clk ; None ; None ; 1.073 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[3] ; current_state[1] ; clk ; clk ; None ; None ; 0.871 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state[3] ; current_state[3] ; clk ; clk ; None ; None ; 0.866 ns ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+---------+------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+---------+------------------+----------+
; N/A ; None ; 5.571 ns ; eoc ; current_state[0] ; clk ;
; N/A ; None ; 5.569 ns ; eoc ; current_state[2] ; clk ;
; N/A ; None ; 2.342 ns ; data[5] ; regq[5] ; clk ;
; N/A ; None ; 0.779 ns ; data[0] ; regq[0] ; clk ;
; N/A ; None ; 0.651 ns ; data[1] ; regq[1] ; clk ;
; N/A ; None ; -0.360 ns ; data[7] ; regq[7] ; clk ;
; N/A ; None ; -0.431 ns ; data[4] ; regq[4] ; clk ;
; N/A ; None ; -0.523 ns ; data[3] ; regq[3] ; clk ;
; N/A ; None ; -0.539 ns ; data[6] ; regq[6] ; clk ;
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