pwm.v

modelsim设计的可调占空比的方波程式

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:16:28 10/22/2006 
// Design Name: 
// Module Name:    pwm 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
//pwm_t :pwm reg time
`define Rcly_end Rcly[4]
`define Rhight_end Rhight[4]


//module pwm(clk, pwm_r, pwmout);
module pwm(pwmout,clk);
    input clk;
    //output[20:0] pwm_r;
    output pwmout;
//	 output pwmout2;
	 //output pwmout3;
//	 output sl;
	 
//reg[19:0] pwm_r;
//reg [23:0] count;


//reg state;

//reg pwm_clk,p2,p3;
wire gclk;
wire gclk2;
wire gclk3;

//assign state[0]=count[21];
/*assign pwmout=pwm_clk;
assign pwmout2=p2;
assign pwmout3=p3;
assign sl=0;
*/
reg pwm;
//reg [1:0] state;
reg [23:0]Rcly_temp,Rcly,Rhight_temp,Rhight;

assign pwmout=pwm;
initial
	begin
      Rcly_temp<=6'h0;
      Rcly<=6'h0;
      Rhight_temp<=6'h2;
      Rhight<=6'h0;
      pwm=1;
      
	end
	
	
and gcly(gclk2,!`Rcly_end,clk);
always @(posedge gclk2)
	begin
		Rcly=Rcly+1;
		$display("Rcly=%h",Rcly);
	end

       
and ghight(gclk3,!`Rhight_end,clk);
always @(posedge gclk3)
   begin
       Rhight=Rhight+1;
       $display("Rhight=%h",Rhight);
        
   end
          
//assign state={`Rcly_end,`Rhight_end};

//--------------------------------------------state
always @(posedge clk)
 begin
      case({`Rcly_end,`Rhight_end})
              2'b0:
              pwm<=1;
              2'b01:
              pwm<=0;
              2'b11:
              fork
                  Rcly<=Rcly_temp;
                  Rhight<=Rhight_temp;
               join
      endcase
$display("state=%b",{`Rcly_end,`Rhight_end}); 
end
endmodule